1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <amdblocks/acpi.h>
4 #include <console/console.h>
5 #include <device/device.h>
6 #include <amdblocks/amd_pci_util.h>
9 #include <soc/southbridge.h>
10 #include <soc/pci_devs.h>
12 #include <commonlib/helpers.h>
13 #include <soc/amd/picasso/chip.h>
16 /* TODO: recheck IRQ tables */
18 /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
19 accessed via I/O ports 0xc00/0xc01. */
20 static const struct fch_irq_routing fch_irq_map
[] = {
25 { PIRQ_SCI
, ACPI_SCI_IRQ
, ACPI_SCI_IRQ
},
26 { PIRQ_SD
, PIRQ_NC
, 16 },
27 { PIRQ_SDIO
, PIRQ_NC
, 16 },
28 { PIRQ_SATA
, PIRQ_NC
, 19 },
29 { PIRQ_EMMC
, PIRQ_NC
, 17 },
32 { PIRQ_I2C3
, 14, 14 },
38 /* The MISC registers are not interrupt numbers */
39 { PIRQ_MISC
, 0xfa, 0x00 },
40 { PIRQ_MISC0
, 0x91, 0x00 },
41 { PIRQ_MISC1
, 0x00, 0x00 },
42 { PIRQ_MISC2
, 0x00, 0x00 },
45 const struct fch_irq_routing
*mb_get_fch_irq_mapping(size_t *length
)
47 *length
= ARRAY_SIZE(fch_irq_map
);
51 static void mainboard_init(void *chip_info
)
53 struct soc_amd_picasso_config
*cfg
= config_of_soc();
55 if (!CONFIG(MANDOLIN_LPC
))
56 cfg
->emmc_config
.timing
= SD_EMMC_EMMC_HS400
;
58 mainboard_program_gpios();
60 /* Re-muxing LPCCLK0 can hang the system if LPC is in use. */
61 if (CONFIG(MANDOLIN_LPC
))
62 printk(BIOS_INFO
, "eMMC not available due to LPC requirement\n");
64 mainboard_program_emmc_gpios();
67 struct chip_operations mainboard_ops
= {
68 .init
= mainboard_init
,