src/mainboard/google/brya/variants/agah/memory.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4
   5 static const struct mb_cfg baseboard_memcfg = {
   6         .type = MEM_TYPE_LP4X,
   7
   8         .rcomp = {
   9                 /* Baseboard uses only 100ohm Rcomp resistors */
  10                 .resistor = 100,
  11
  12                 /* Baseboard Rcomp target values */
  13                 .targets = {40, 30, 30, 30, 30},
  14         },
  15
  16         /* DQ byte map */
  17         .lpx_dq_map = {
  18                 .ddr0 = {
  19                         .dq0 = {  3,  2,  0,  1,  4,  7,  6,  5, },  /* DDR_A_DQ0 */
  20                         .dq1 = { 12, 13, 14, 15,  9, 10,  8, 11, },  /* DDR_A_DQ1 */
  21                 },
  22                 .ddr1 = {
  23                         .dq0 = { 14,  8,  9, 15, 10, 12, 11, 13, },  /* DDR_A_DQ2 */
  24                         .dq1 = {  1,  7,  6,  0,  5,  3,  4,  2, },  /* DDR_A_DQ3 */
  25                 },
  26                 .ddr2 = {
  27                         .dq0 = {  2,  3,  1,  0,  6,  5,  7,  4, },  /* DDR_A_DQ4 */
  28                         .dq1 = { 12, 13, 14, 15, 10, 11,  9,  8, },  /* DDR_A_DQ5 */
  29                 },
  30                 .ddr3 = {
  31                         .dq0 = {  1,  2,  0,  3,  5,  6,  7,  4, },  /* DDR_A_DQ6 */
  32                         .dq1 = { 15, 14, 13, 12, 10,  9,  8, 11, },  /* DDR_A_DQ7 */
  33                 },
  34                 .ddr4 = {
  35                         .dq0 = {  3,  2,  1,  0,  7,  6,  5,  4, },  /* DDR_B_DQ0 */
  36                         .dq1 = { 12, 15, 13, 14,  8,  9, 10, 11, },  /* DDR_B_DQ1 */
  37                 },
  38                 .ddr5 = {
  39                         .dq0 = { 14,  8,  9, 15, 12, 10, 11, 13, },  /* DDR_B_DQ2 */
  40                         .dq1 = {  1,  7,  6,  0,  5,  2,  4,  3, },  /* DDR_B_DQ3 */
  41                 },
  42                 .ddr6 = {
  43                         .dq0 = { 13, 12, 15, 14,  8, 10,  9, 11, },  /* DDR_B_DQ4 */
  44                         .dq1 = {  7,  4,  6,  5,  1,  0,  3,  2, },  /* DDR_B_DQ5 */
  45                 },
  46                 .ddr7 = {
  47                         .dq0 = {  6,  0,  7,  5,  3,  2,  1,  4, },  /* DDR_B_DQ6 */
  48                         .dq1 = { 10,  8, 13, 12,  9, 14, 15, 11, },  /* DDR_B_DQ7 */
  49                 },
  50         },
  51
  52         /* DQS CPU<>DRAM map */
  53         .lpx_dqs_map = {
  54                 .ddr0 = { .dqs0 = 0, .dqs1 = 1 },
  55                 .ddr1 = { .dqs0 = 1, .dqs1 = 0 },
  56                 .ddr2 = { .dqs0 = 0, .dqs1 = 1 },
  57                 .ddr3 = { .dqs0 = 0, .dqs1 = 1 },
  58                 .ddr4 = { .dqs0 = 0, .dqs1 = 1 },
  59                 .ddr5 = { .dqs0 = 1, .dqs1 = 0 },
  60                 .ddr6 = { .dqs0 = 1, .dqs1 = 0 },
  61                 .ddr7 = { .dqs0 = 0, .dqs1 = 1 },
  62         },
  63
  64         .LpDdrDqDqsReTraining = 1,
  65
  66         .ect = 1, /* Enable Early Command Training */
  67 };
  68
  69 const struct mb_cfg *__weak variant_memory_params(void)
  70 {
  71         return &baseboard_memcfg;
  72 }