src/mainboard/google/brya/variants/anraggar/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A7  : NC ==> LTE_Present */
  11         PAD_CFG_GPI(GPP_A7, NONE, DEEP),
  12         /* A8  : GPP_A8 ==> WWAN_RF_DISABLE_ODL */
  13         PAD_CFG_GPO(GPP_A8, 1, DEEP),
  14         /* A18 : NC ==> HDMI_HPD_SRC*/
  15         PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  16
  17         /* A20 : DDSP_HPD2 ==> NC */
  18         PAD_NC_LOCK(GPP_A20, NONE, LOCK_CONFIG),
  19         /* A21 : GPP_A21 ==> NC */
  20         PAD_NC_LOCK(GPP_A21, NONE, LOCK_CONFIG),
  21         /* A22 : GPP_A22 ==> NC */
  22         PAD_NC_LOCK(GPP_A22, NONE, LOCK_CONFIG),
  23
  24         /* B5  : I2C2_SDA ==> MIPI_WCAM_SDA */
  25         PAD_CFG_NF_LOCK(GPP_B5, NONE, NF2, LOCK_CONFIG),
  26         /* B6  : I2C2_SCL ==> MIPI_WCAM_SCL */
  27         PAD_CFG_NF_LOCK(GPP_B6, NONE, NF2, LOCK_CONFIG),
  28
  29         /* B11 : NC ==> EN_PP3300_WLAN_X*/
  30         PAD_CFG_GPO(GPP_B11, 0, DEEP),
  31
  32         /* D6 : NC ==> WWAN_PWR_ENABLE */
  33         PAD_CFG_GPO(GPP_D6, 1, DEEP),
  34         /* D8  : SRCCLKREQ3# ==> NC */
  35         PAD_NC_LOCK(GPP_D8, NONE, LOCK_CONFIG),
  36         /* D13 : NC ==> EN_PP1800_WCAM_X */
  37         PAD_CFG_GPO_LOCK(GPP_D13, 1, LOCK_CONFIG),
  38
  39         /* E20 : DDP2_CTRLCLK ==> NC */
  40         PAD_NC_LOCK(GPP_E20, NONE, LOCK_CONFIG),
  41         /* E21 : DDP2_CTRLDATA ==> GPP_E21_STRAP */
  42         PAD_NC_LOCK(GPP_E21, NONE, LOCK_CONFIG),
  43
  44         /* H22 : IMGCLKOUT3 ==> WCAM_MCLK_R */
  45         PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1),
  46         /* H23 : WWAN_SAR_DETECT_ODL */
  47         PAD_CFG_GPO(GPP_H23, 1, DEEP),
  48
  49         /* F11 : NC ==> WWAN_PWR_ON */
  50         PAD_CFG_GPO_LOCK(GPP_F11, 1, LOCK_CONFIG),
  51         /* F12 : GSXDOUT ==> WWAN_RST_L */
  52         PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG),
  53         /* F18 : THC1_SPI2_INT# ==> EN_PP2800_AFVDD */
  54         PAD_CFG_GPO(GPP_F18, 0, DEEP),
  55         /* F23 : V1P05_CTRL ==> NC*/
  56         PAD_NC_LOCK(GPP_F23, NONE, LOCK_CONFIG),
  57
  58
  59         /* H12 : UART0_RTS# ==> NC*/
  60         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
  61         /* H13 : UART0_CTS# ==> NC */
  62         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
  63         /* H15 : DDPB_CTRLCLK ==> HDMI_DDC_SCL */
  64         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
  65         /* H17 : DDPB_CTRLDATA ==> HDMI_DDC_SDA */
  66         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1),
  67
  68         /* R6 : DMIC_CLK_A_1A ==> NC */
  69         PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
  70         /* R7 : DMIC_DATA_1A ==> NC */
  71         PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
  72
  73         /* Configure the virtual CNVi Bluetooth I2S GPIO pads */
  74         /* BT_I2S_BCLK */
  75         PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3),
  76         /* BT_I2S_SYNC */
  77         PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3),
  78         /* BT_I2S_SDO */
  79         PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3),
  80         /* BT_I2S_SDI */
  81         PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3),
  82         /* SSP2_SCLK */
  83         PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1),
  84         /* SSP2_SFRM */
  85         PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1),
  86         /* SSP_TXD */
  87         PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1),
  88         /* SSP_RXD */
  89         PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1),
  90 };
  91
  92 /* Early pad configuration in bootblock */
  93 static const struct pad_config early_gpio_table[] = {
  94         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR_X */
  95         PAD_CFG_GPO(GPP_C0, 1, DEEP),
  96         /* C1  : SMBDATA ==> TCHSCR_RST_L */
  97         PAD_CFG_GPO(GPP_C1, 1, DEEP),
  98
  99         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 100         PAD_CFG_GPO(GPP_H20, 0, DEEP),
 101         /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */
 102         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 103         /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */
 104         PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP),
 105
 106         /* F11 : NC ==> WWAN_PWR_ON */
 107         PAD_CFG_GPO(GPP_F11, 1, DEEP),
 108         /* F12 : GSXDOUT ==> WWAN_RST_L */
 109         PAD_CFG_GPO(GPP_F12, 0, DEEP),
 110         /* D6 : NC ==> WWAN_PWR_ENABLE */
 111         PAD_CFG_GPO(GPP_D6, 1, DEEP),
 112
 113         /* H4  : I2C0_SDA ==> SOC_I2C_GSC_SDA */
 114         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 115         /* H5  : I2C0_SCL ==> SOC_I2C_GSC_SCL */
 116         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 117
 118         /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */
 119         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 120         /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */
 121         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 122 };
 123
 124 static const struct pad_config romstage_gpio_table[] = {
 125         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 126         PAD_CFG_GPO(GPP_H20, 1, DEEP),
 127 };
 128
 129 const struct pad_config *variant_gpio_override_table(size_t *num)
 130 {
 131         *num = ARRAY_SIZE(override_gpio_table);
 132         return override_gpio_table;
 133 }
 134
 135 const struct pad_config *variant_early_gpio_table(size_t *num)
 136 {
 137         *num = ARRAY_SIZE(early_gpio_table);
 138         return early_gpio_table;
 139 }
 140
 141 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 142 {
 143         *num = ARRAY_SIZE(romstage_gpio_table);
 144         return romstage_gpio_table;
 145 }