src/mainboard/google/brya/variants/banshee/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A0 thru A5, A9 and A10 come configured out of reset, do not touch */
  11         /* A0  : ESPI_IO0 ==> ESPI_IO_0 */
  12         /* A1  : ESPI_IO1 ==> ESPI_IO_1 */
  13         /* A2  : ESPI_IO2 ==> ESPI_IO_2 */
  14         /* A3  : ESPI_IO3 ==> ESPI_IO_3 */
  15         /* A4  : ESPI_CS# ==> ESPI_CS_L */
  16         /* A5  : ESPI_ALERT0# ==> NC */
  17         /* A6  : ESPI_ALERT1# ==> NC */
  18         PAD_NC(GPP_A6, NONE),
  19         /* A7  : SRCCLK_OE7# ==> NC */
  20         PAD_NC(GPP_A7, NONE),
  21         /* A8  : SRCCLKREQ7# ==> NC */
  22         PAD_NC(GPP_A8, NONE),
  23         /* A9  : ESPI_CLK ==> ESPI_CLK */
  24         /* A10 : ESPI_RESET# ==> ESPI_PCH_RST_EC_L */
  25         /* A11 : PMC_I2C_SDA ==> EN_SPKR_PA */
  26         /* A12 : SATAXPCIE1 ==> EN_PP3300_SSD */
  27         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  28         /* A14 : USB_OC1# ==> USB_C1_OC_ODL */
  29         /* A15 : USB_OC2# ==> USB_C2_OC_ODL */
  30         /* A16 : USB_OC3# ==> USB_C3_OC_ODL */
  31         /* A17 : DISP_MISCC ==> EN_FCAM_PWR */
  32         /* A18 : DDSP_HPDB ==> NC */
  33         PAD_NC(GPP_A18, NONE),
  34         /* A19 : DDSP_HPD1 ==> NC */
  35         PAD_NC(GPP_A19, NONE),
  36         /* A20 : DDSP_HPD2 ==> NC */
  37         PAD_NC(GPP_A20, NONE),
  38         /* A21 : DDPC_CTRCLK ==> NC */
  39         PAD_NC(GPP_A21, NONE),
  40         /* A22 : DDPC_CTRLDATA ==> NC */
  41         PAD_NC(GPP_A22, NONE),
  42         /* A23 : ESPI_CS1# ==> AUD_HP_INT_L */
  43
  44         /* B0  : SOC_VID0 */
  45         /* B1  : SOC_VID1 */
  46         /* B2  : VRALERT# ==> NC */
  47         PAD_NC_LOCK(GPP_B2, NONE, LOCK_CONFIG),
  48         /* B3  : PROC_GP2 ==> NC */
  49         PAD_NC_LOCK(GPP_B3, NONE, LOCK_CONFIG),
  50         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  51         /* B5  : ISH_I2C0_SDA ==> NC */
  52         PAD_NC_LOCK(GPP_B5, NONE, LOCK_CONFIG),
  53         /* B6  : ISH_I2C0_SCL ==> NC */
  54         PAD_NC_LOCK(GPP_B6, NONE, LOCK_CONFIG),
  55         /* B7  : ISH_12C1_SDA ==> NC */
  56         PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG),
  57         /* B8  : ISH_I2C1_SCL ==> NC */
  58         PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG),
  59         /* B9  : NC */
  60         /* B10 : NC */
  61         /* B11 : PMCALERT# ==> EN_PP3300_WLAN */
  62         /* B12 : SLP_S0# ==> SLP_S0_L */
  63         /* B13 : PLTRST# ==> PLT_RST_L */
  64         /* B14 : SPKR ==> GPP_B14_STRAP */
  65         /* B15 : TIME_SYNC0 ==> NC */
  66         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  67         /* B16 : I2C5_SDA ==> PCH_I2C_TCHPAD_SDA */
  68         /* B17 : I2C5_SCL ==> PCH_I2C_TCHPAD_SCL */
  69         /* B18 : ADR_COMPLETE ==> GPP_B18_STRAP */
  70         /* B19 : NC */
  71         /* B20 : NC */
  72         /* B21 : NC */
  73         /* B22 : NC */
  74         /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */
  75
  76         /* C0  : SMBCLK ==> DDR_SMB_CLK */
  77         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
  78         /* C1  : SMBDATA ==> DDR_SMB_DATA */
  79         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
  80         /* C2  : SMBALERT# ==> GPP_C2_STRAP */
  81         /* C3 : SML0CLK ==> NC */
  82         PAD_NC(GPP_C3, NONE),
  83         /* C4 : SML0DATA ==> NC */
  84         PAD_NC(GPP_C4, NONE),
  85         /* C5  : SML0ALERT# ==> GPP_C5_BOOT_STRAP0 */
  86         /* C6  : SML1CLK ==> NC */
  87         PAD_NC(GPP_C6, NONE),
  88         /* C7  : SML1DATA ==> NC */
  89         PAD_NC(GPP_C7, NONE),
  90
  91         /* D0  : ISH_GP0 ==> NC */
  92         PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
  93         /* D1  : ISH_GP1 ==> NC */
  94         PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
  95         /* D2  : ISH_GP2 ==> NC */
  96         PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
  97         /* D3  : ISH_GP3 ==> NC */
  98         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  99         /* D4  : IMGCLKOUT0 ==> BT_DISABLE_L */
 100         /* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
 101         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 102         /* D6  : SRCCLKREQ1# ==> NC */
 103         PAD_NC(GPP_D6, NONE),
 104         /* D7  : SRCCLKREQ2# ==> WLAN_CLKREQ_ODL */
 105         /* D8  : SRCCLKREQ3# ==> NC */
 106         PAD_NC(GPP_D8, NONE),
 107         /* D9  : ISH_SPI_CS# ==> USB_C2_LSX_TX */
 108         /* D10 : ISH_SPI_CLK ==> USB_C2_LSX_RX_STRAP */
 109         /* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */
 110         PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG),
 111         /* D12 : ISH_SPI_MOSI ==> USB_C3_LSX_RX */
 112         PAD_CFG_NF_LOCK(GPP_D12, NONE, NF4, LOCK_CONFIG),
 113         /* D13 : ISH_UART0_RXD ==> NC */
 114         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
 115         /* D14 : ISH_UART0_TXD ==> NC */
 116         PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
 117         /* D15 : ISH_UART0_RTS# ==> NC */
 118         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
 119         /* D16 : ISH_UART0_CTS# ==> NC */
 120         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
 121         /* D17 : UART1_RXD ==> NC */
 122         PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
 123         /* D18 : UART1_TXD ==> USI_RST_L */
 124         PAD_CFG_GPO_LOCK(GPP_D18, 0, LOCK_CONFIG),
 125         /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
 126
 127         /* E0  : SATAXPCIE0 ==> NC */
 128         PAD_NC(GPP_E0, NONE),
 129         /* E1  : THC0_SPI1_IO2 ==> NC */
 130         PAD_NC_LOCK(GPP_E1, NONE, LOCK_CONFIG),
 131         /* E2  : THC0_SPI1_IO3 ==> NC */
 132         PAD_NC_LOCK(GPP_E2, NONE, LOCK_CONFIG),
 133         /* E3  : PROC_GP0 ==> NC */
 134         PAD_NC(GPP_E3, NONE),
 135         /* E4  : SATA_DEVSLP0 ==> USB4_BB_RT_FORCE_PWR */
 136         /* E5  : SATA_DEVSLP1 ==> NC */
 137         PAD_NC(GPP_E5, NONE),
 138         /* E6  : THC0_SPI1_RST# ==> GPPE6_STRAP */
 139         /* E7  : PROC_GP1 ==> NC */
 140         PAD_NC(GPP_E7, NONE),
 141         /* E8  : SLP_DRAM# ==> WIFI_DISABLE_L */
 142         /* E9  : USB_OC0# ==> USB_C0_OC_ODL */
 143         /* E10 : THC0_SPI1_CS# ==> NC */
 144         PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
 145         /* E11 : THC0_SPI1_CLK ==> NC */
 146         PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG),
 147         /* E12 : THC0_SPI1_IO1 ==> NC */
 148         PAD_NC_LOCK(GPP_E12, NONE, LOCK_CONFIG),
 149         /* E13 : THC0_SPI1_IO2 ==> NC */
 150         PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
 151         /* E14 : DDSP_HPDA ==> SOC_EDP_HPD */
 152         /* E15 : RSVD_TP ==> PCH_WP_OD */
 153         /* E16 : RSVD_TP ==> NC */
 154         PAD_NC(GPP_E16, NONE),
 155         /* E17 : THC0_SPI1_INT# ==> NC */
 156         PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
 157         /* E18 : DDP1_CTRLCLK ==> USB_C0_LSX_SOC_TX */
 158         /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */
 159         /* E20 : DDP2_CTRLCLK ==> USB_C1_LSX_SOC_TX */
 160         /* E21 : DDP2_CTRLDATA ==> USB_C1_LSX_SOC_RX_STRAP */
 161         /* E22 : DDPA_CTRLCLK ==> NC */
 162         PAD_NC(GPP_E22, NONE),
 163         /* E23 : DDPA_CTRLDATA ==> NC */
 164         PAD_NC(GPP_E23, NONE),
 165
 166         /* F0  : CNV_BRI_DT ==> CNV_BRI_DT_STRAP */
 167         /* F1  : CNV_BRI_RSP ==> CNV_BRI_RSP */
 168         /* F2  : CNV_RGI_DT ==> CNV_RGI_DT_STRAP */
 169         /* F3  : CNV_RGI_RSP ==> CNV_RGI_RSP */
 170         /* F4  : CNV_RF_RESET# ==> CNV_RF_RST_L */
 171         /* F5  : MODEM_CLKREQ ==> CNV_CLKREQ0 */
 172         /* F6  : CNV_PA_BLANKING ==> NC */
 173         PAD_NC(GPP_F6, NONE),
 174         /* F7  : GPPF7_STRAP */
 175         /* F8  : NC */
 176         /* F9  : BOOTMPC ==> SLP_S0_GATE_R */
 177         /* F10 : GPPF10_STRAP */
 178         /* F11 : THC1_SPI2_CLK ==> NC */
 179         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
 180         /* F12 : GSXDOUT ==> NC */
 181         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 182         /* F13 : GSXDOUT ==> NC */
 183         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 184         /* F14 : GSXDIN ==> TCHPAD_INT_ODL */
 185         /* F15 : GSXSRESET# ==> NC */
 186         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 187         /* F16 : GSXCLK ==> NC */
 188         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 189         /* F17 : THC1_SPI2_RST# ==> EC_PCH_INT_ODL */
 190         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 191         /* F19 : SRCCLKREQ6# ==> CAM_SW */
 192         PAD_CFG_GPI_INT(GPP_F19, NONE, PLTRST, EDGE_BOTH),
 193         /* F20 : EXT_PWR_GATE# ==> NC */
 194         PAD_NC(GPP_F20, NONE),
 195         /* F21 : EXT_PWR_GATE2# ==> NC */
 196         PAD_NC(GPP_F21, NONE),
 197         /* F22 : NC ==> MIC_SW */
 198         PAD_CFG_GPI_GPIO_DRIVER(GPP_F22, NONE, DEEP),
 199         /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */
 200         PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1),
 201
 202         /* H0  : GPPH0_BOOT_STRAP1 */
 203         /* H1  : GPPH1_BOOT_STRAP2 */
 204         /* H2  : GPPH2_BOOT_STRAP3 */
 205         /* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
 206         /* H4  : I2C0_SDA ==> PCH_I2C_AUD_SDA */
 207         /* H5  : I2C0_SCL ==> PCH_I2C_AUD_SCL */
 208         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 209         PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
 210         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 211         PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
 212         /* H8  : I2C4_SDA ==> NC */
 213         PAD_NC(GPP_H8, NONE),
 214         /* H9  : I2C4_SCL ==> NC */
 215         PAD_NC(GPP_H9, NONE),
 216         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 217         /* H12 : I2C7_SDA ==> NC */
 218         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
 219         /* H13 : I2C7_SCL ==> NC */
 220         PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
 221         /* H14 : NC */
 222         /* H15 : DDPB_CTRLCLK ==> NC */
 223         PAD_NC(GPP_H15, NONE),
 224         /* H16 : NC */
 225         /* H17 : DDPB_CTRLDATA ==> NC */
 226         PAD_NC(GPP_H17, NONE),
 227         /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE_L */
 228         /* H19 : SRCCLKREQ4# ==> NC */
 229         PAD_NC(GPP_H19, NONE),
 230         /* H20 : IMGCLKOUT1 ==> WLAN_PERST_L */
 231         /* H21 : IMGCLKOUT2 ==>  NC */
 232         PAD_NC(GPP_H21, NONE),
 233         /* H22 : IMGCLKOUT3 ==> NC */
 234         PAD_NC(GPP_H22, NONE),
 235         /* H23 : SRCCLKREQ5# ==> NC */
 236         PAD_NC(GPP_H23, NONE),
 237
 238         /* R0 : HDA_BCLK ==> I2S_HP_SCLK_R */
 239         /* R1 : HDA_SYNC ==> I2S_HP_SFRM_R */
 240         /* R2 : HDA_SDO ==> I2S_PCH_TX_HP_RX_STRAP */
 241         /* R3 : HDA_SDIO ==> I2S_PCH_RX_HP_TX */
 242         /* R4 : HDA_RST# ==> NC */
 243         PAD_NC(GPP_R4, NONE),
 244         /* R5 : HDA_SDI1 ==> NC */
 245         PAD_NC(GPP_R5, NONE),
 246         /* R6 : I2S2_TXD ==> NC */
 247         PAD_NC(GPP_R6, NONE),
 248         /* R7 : I2S2_RXD ==> NC */
 249         PAD_NC(GPP_R7, NONE),
 250
 251         /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */
 252         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 253         /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */
 254         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 255         /* S2 : SNDW1_CLK ==> I2S_PCH_TX_SPKR_RX_R */
 256         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 257         /* S3 : SNDW1_DATA ==> NC */
 258         PAD_NC(GPP_S3, NONE),
 259         /* S4 : SNDW2_CLK ==> NC */
 260         PAD_NC(GPP_S4, NONE),
 261         /* S5 : SNDW2_DATA ==> NC */
 262         PAD_NC(GPP_S5, NONE),
 263         /* S6 : SNDW3_CLK ==> DMIC_CLK0_R */
 264         /* S7 : SNDW3_DATA ==> DMIC_DATA0_R */
 265
 266         /* GPD11: LANPHYC ==> NC */
 267         PAD_NC(GPD11, NONE),
 268 };
 269
 270 /* Early pad configuration in bootblock */
 271 static const struct pad_config early_gpio_table[] = {
 272         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 273         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 274         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 275         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 276         /* A12 : SATAXPCIE1 ==> EN_PP3300_SSD */
 277         PAD_CFG_GPO(GPP_A12, 1, DEEP),
 278         /* E15 : RSVD_TP ==> PCH_WP_OD */
 279         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 280         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 281         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 282         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 283         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 284         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 285         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 286         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 287         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 288         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 289         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 290
 291         /* CPU PCIe VGPIO for PEG60 */
 292         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 293         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 294         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 295         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 296         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 297         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 298         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 299         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 300         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 301         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 302         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 303         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 304         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 305         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 306         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 307         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 308         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 309         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 310         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 311         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 312 };
 313
 314 static const struct pad_config romstage_gpio_table[] = {
 315         /*
 316          * B4  : PROC_GP3 ==> SSD_PERST_L
 317          * B4 is programmed here so that it is sequenced after EN_PP3300_SSD.
 318          */
 319         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 320 };
 321
 322 const struct pad_config *variant_gpio_override_table(size_t *num)
 323 {
 324         *num = ARRAY_SIZE(override_gpio_table);
 325         return override_gpio_table;
 326 }
 327
 328 const struct pad_config *variant_early_gpio_table(size_t *num)
 329 {
 330         *num = ARRAY_SIZE(early_gpio_table);
 331         return early_gpio_table;
 332 }
 333
 334 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 335 {
 336         *num = ARRAY_SIZE(romstage_gpio_table);
 337         return romstage_gpio_table;
 338 }