src/mainboard/google/brya/variants/brya0/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/variants.h>
   4 #include <boardid.h>
   5 #include <soc/gpio.h>
   6
   7 static const struct pad_config board_id0_1_overrides[] = {
   8         /* B2  : VRALERT# ==> NC */
   9         PAD_NC(GPP_B2, NONE),
  10         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
  11         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  12         /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
  13         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  14         /* B15 : TIME_SYNC0 ==> NC */
  15         PAD_NC(GPP_B15, NONE),
  16         /* C3  : SML0CLK ==> NC */
  17         PAD_NC(GPP_C3, NONE),
  18         /* C4  : SML0DATA ==> NC */
  19         PAD_NC(GPP_C4, NONE),
  20         /* D13 : ISH_UART0_RXD ==> PCH_I2C_CAM_SDA */
  21         PAD_CFG_NF(GPP_D13, NONE, DEEP, NF3),
  22         /* D14 : ISH_UART0_TXD ==> PCH_I2C_CAM_SCL */
  23         PAD_CFG_NF(GPP_D14, NONE, DEEP, NF3),
  24         /* F19 : SRCCLKREQ6# ==> WWAN_SIM1_DET_OD */
  25         PAD_CFG_GPI(GPP_F19, UP_20K, DEEP),
  26         /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */
  27         PAD_CFG_GPO(GPP_F20, 0, DEEP),
  28         /* F21 : EXT_PWR_GATE2# ==> WAKE_ON_WWAN_ODL */
  29         PAD_NC(GPP_F21, NONE),
  30         /* H21 : IMGCLKOUT2 ==> WLAN_INT_L */
  31         PAD_CFG_GPI_APIC(GPP_H21, NONE, DEEP, EDGE_SINGLE, NONE),
  32         /* GPD2: LAN_WAKE# ==> NC */
  33         PAD_NC(GPD2, NONE),
  34 };
  35
  36 /* Early pad configuration in bootblock for board id < 2 */
  37 static const struct pad_config early_gpio_table[] = {
  38         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  39         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  40         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
  41         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
  42         /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
  43         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
  44         /*
  45          * D1  : ISH_GP1 ==> FP_RST_ODL
  46          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
  47          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
  48          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
  49          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
  50          * FPMCU not working after a S3 resume. This is a known issue.
  51          */
  52         PAD_CFG_GPO(GPP_D1, 0, DEEP),
  53         /* D2  : ISH_GP2 ==> EN_FP_PWR */
  54         PAD_CFG_GPO(GPP_D2, 1, DEEP),
  55         /* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
  56         PAD_CFG_GPO(GPP_E0, 0, DEEP),
  57         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
  58         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
  59         /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
  60         PAD_CFG_GPO(GPP_E16, 0, DEEP),
  61         /* E15 : RSVD_TP ==> PCH_WP_OD */
  62         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
  63         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
  64         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
  65         /* F21 : EXT_PWR_GATE2# ==> NC */
  66         PAD_NC(GPP_F21, NONE),
  67         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
  68         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
  69         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
  70         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
  71         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
  72         PAD_NC(GPP_H13, UP_20K),
  73 };
  74
  75 /* Early pad configuration in bootblock for board id 2 */
  76 static const struct pad_config early_gpio_table_id2[] = {
  77         /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
  78         PAD_CFG_GPO(GPP_A12, 1, DEEP),
  79         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  80         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  81         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  82         PAD_CFG_GPO(GPP_B4, 0, DEEP),
  83         /* B7  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
  84         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF2),
  85         /* B8  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
  86         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF2),
  87         /*
  88          * D1  : ISH_GP1 ==> FP_RST_ODL
  89          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
  90          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
  91          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
  92          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
  93          * FPMCU not working after a S3 resume. This is a known issue.
  94          */
  95         PAD_CFG_GPO(GPP_D1, 0, DEEP),
  96         /* D2  : ISH_GP2 ==> EN_FP_PWR */
  97         PAD_CFG_GPO(GPP_D2, 1, DEEP),
  98         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
  99         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 100         /* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
 101         PAD_CFG_GPO(GPP_E0, 0, DEEP),
 102         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 103         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 104         /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
 105         PAD_CFG_GPO(GPP_E16, 0, DEEP),
 106         /* E15 : RSVD_TP ==> PCH_WP_OD */
 107         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 108         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 109         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 110         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
 111         PAD_CFG_GPO(GPP_F21, 0, DEEP),
 112         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 113         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 114         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 115         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 116         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 117         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 118 };
 119
 120 /* Early pad configuration in bootblock for board id 4 */
 121 static const struct pad_config early_gpio_table_id4[] = {
 122         /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
 123         PAD_CFG_GPO(GPP_A12, 1, DEEP),
 124         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 125         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 126         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 127         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 128         /* H6  : ISH_12C1_SDA ==> PCH_I2C_TPM_SDA */
 129         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 130         /* H7  : ISH_12C1_SCL ==> PCH_I2C_TPM_SCL */
 131         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 132         /*
 133          * D1  : ISH_GP1 ==> FP_RST_ODL
 134          * FP_RST_ODL comes out of reset as hi-z and does not have an external
 135          * pull-down. To ensure proper power sequencing for the FPMCU device,
 136          * reset signal is driven low early on in bootblock, followed by
 137          * enabling of power. Reset signal is deasserted later on in ramstage.
 138          * Since reset signal is asserted in bootblock, it results in FPMCU not
 139          * working after a S3 resume. This is a known issue.
 140          */
 141         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 142         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 143         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 144         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 145         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 146         /* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
 147         PAD_CFG_GPO(GPP_E0, 0, DEEP),
 148         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 149         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 150         /* E16 : RSVD_TP ==> WWAN_RST_L (updated in ramstage) */
 151         PAD_CFG_GPO(GPP_E16, 0, DEEP),
 152         /* E15 : RSVD_TP ==> PCH_WP_OD */
 153         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 154         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 155         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 156         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
 157         PAD_CFG_GPO(GPP_F21, 0, DEEP),
 158         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 159         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 160         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 161         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 162         /* H13 : I2C7_SCL ==> EN_PP3300_SD */
 163         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 164 };
 165
 166 static const struct pad_config romstage_gpio_table[] = {
 167         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 168         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 169
 170         /* Enable touchscreen, hold in reset */
 171         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 172         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 173         /* C1  : SMBDATA ==> USI_RST_L */
 174         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 175
 176         /* D1  : ISH_GP1 ==> FP_RST_ODL */
 177         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 178         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 179         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 180
 181         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 182         PAD_CFG_GPO(GPP_F21, 1, DEEP),
 183 };
 184
 185 const struct pad_config *variant_gpio_override_table(size_t *num)
 186 {
 187         const uint32_t id = board_id();
 188         if (id == BOARD_ID_UNKNOWN || id < 2) {
 189                 *num = ARRAY_SIZE(board_id0_1_overrides);
 190                 return board_id0_1_overrides;
 191         }
 192
 193         *num = 0;
 194         return NULL;
 195 }
 196
 197 const struct pad_config *variant_early_gpio_table(size_t *num)
 198 {
 199         const uint32_t id = board_id();
 200         if (id == BOARD_ID_UNKNOWN || id < 2) {
 201                 *num = ARRAY_SIZE(early_gpio_table);
 202                 return early_gpio_table;
 203         } else if (id >= 4) {
 204                 *num = ARRAY_SIZE(early_gpio_table_id4);
 205                 return early_gpio_table_id4;
 206         }
 207
 208         *num = ARRAY_SIZE(early_gpio_table_id2);
 209         return early_gpio_table_id2;
 210 }
 211
 212 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 213 {
 214         *num = ARRAY_SIZE(romstage_gpio_table);
 215         return romstage_gpio_table;
 216 }