src/mainboard/google/brya/variants/constitution/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <gpio.h>
   6
   7 /* Pad configuration in ramstage */
   8 static const struct pad_config override_gpio_table[] = {
   9         /* A23 : ESPI_CS1# ==> NC */
  10         PAD_NC_LOCK(GPP_A23, NONE, LOCK_CONFIG),
  11         /* B7  : ISH_12C1_SDA ==> PCH_I2C_MISCB_SDA */
  12         PAD_CFG_NF_LOCK(GPP_B7, NONE, NF2, LOCK_CONFIG),
  13         /* B8  : ISH_I2C1_SCL ==> PCH_I2C_MISCB_SCL */
  14         PAD_CFG_NF_LOCK(GPP_B8, NONE, NF2, LOCK_CONFIG),
  15         /* B16 : I2C5_SDA ==> PCH_I2C_TPU_SDA */
  16         PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG),
  17         /* B17 : I2C5_SCL ==> PCH_I2C_TPU_SCL */
  18         PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG),
  19
  20         /* D0  : ISH_GP0 ==> DEV_MODE_CTRL */
  21         PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
  22         /* D1  : ISH_GP1 ==> HDMI_IN_PLUGIN */
  23         PAD_CFG_GPO_LOCK(GPP_D1, 1, LOCK_CONFIG),
  24         /* D2  : ISH_GP2 ==> REC_MODE */
  25         PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
  26         /* D3  : ISH_GP3 ==> QSPI_MR_N */
  27         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  28         /* D9  : ISH_SPI_CS# ==> NC */
  29         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  30         /* D10  : ISH_SPI_CS# ==> NC */
  31         PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
  32         /* D13  : ISH_UART0_RXD ==> PCH_I2C_U3A0_SDA */
  33         PAD_CFG_NF_LOCK(GPP_D13, NONE, NF3, LOCK_CONFIG),
  34         /* D14  : ISH_UART0_TXD ==> PCH_I2C_U3A0_SCL */
  35         PAD_CFG_NF_LOCK(GPP_D14, NONE, NF3, LOCK_CONFIG),
  36         /* D15  : ISH_UART0_RTS# ==> BOOT_SET_N */
  37         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  38         /* D16  : ISH_UART0_CTS# ==> BOOT_IND */
  39         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  40         /* D17  : UART1_RXD ==> PCH_UART1_RX_ADB_TX */
  41         PAD_CFG_NF_LOCK(GPP_D17, NONE, NF1, LOCK_CONFIG),
  42         /* D18  : UART1_TXD ==> PCH_UART1_TX_ADB_RX */
  43         PAD_CFG_NF_LOCK(GPP_D18, NONE, NF1, LOCK_CONFIG),
  44         /* D19  : ISH_SPI_MOSI ==> NC */
  45         PAD_NC_LOCK(GPP_D19, NONE, LOCK_CONFIG),
  46
  47         /* E1  : THC0_SPI1_IO2 ==> NC */
  48         PAD_NC_LOCK(GPP_E1, NONE, LOCK_CONFIG),
  49         /* E2  : THC0_SPI1_IO3 ==> LAN_I350_WAKE# */
  50         PAD_CFG_GPI_IRQ_WAKE(GPP_E2, NONE, DEEP, LEVEL, INVERT),
  51         /* E12 : THC0_SPI1_IO1 ==> TPU_RST_PIN40 */
  52         PAD_CFG_GPO(GPP_E12, 1, DEEP),
  53         /* E13 : THC0_SPI1_IO2 ==> TPU_RST_PIN42 */
  54         PAD_CFG_GPO(GPP_E13, 1, DEEP),
  55         /* E14 : DDSP_HPDA ==> HDMIA_HPD */
  56         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
  57         /* E20 : DDP2_CTRLCLK ==> HDMIA_CTRLCLK */
  58         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
  59         /* E21 : DDP2_CTRLDATA ==> HDMIA_CTRLDATA_STRAP */
  60         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
  61
  62         /* F11 : THC1_SPI2_CLK ==> MEM_CH_SEL */
  63         PAD_CFG_GPI_LOCK(GPP_F11, NONE, LOCK_CONFIG),
  64         /* F12 : GSXDOUT ==> MEM_STRAP_1 */
  65         PAD_CFG_GPI_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  66         /* F13 : GSXDOUT ==> MEM_STRAP_2 */
  67         PAD_CFG_GPI_LOCK(GPP_F13, NONE, LOCK_CONFIG),
  68         /* F15 : GSXSRESET# ==> MEM_STRAP_3 */
  69         PAD_CFG_GPI_LOCK(GPP_F15, NONE, LOCK_CONFIG),
  70         /* F16 : GSXCLK ==> MEM_STRAP_0 */
  71         PAD_CFG_GPI_LOCK(GPP_F16, NONE, LOCK_CONFIG),
  72
  73         /* H4  : I2C0_SDA ==> PCH_I2C_AUD_SDA */
  74         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
  75         /* H5  : I2C0_SCL ==> PCH_I2C_AUD_SCL */
  76         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
  77         /* H12 : I2C7_SDA ==> PCH_I2C_U3A1_SDA */
  78         PAD_CFG_NF(GPP_H12, NONE, DEEP, NF1),
  79         /* H13 : I2C7_SCL ==> PCH_I2C_U3A1_SCL */
  80         PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1),
  81         /* H19 : SRCCLKREQ4# ==> M2_TPU1_CLKREQ_ODL */
  82         PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1),
  83
  84         /* R0 : HDA_BCLK ==> NC */
  85         PAD_NC_LOCK(GPP_R0, NONE, LOCK_CONFIG),
  86         /* R1 : HDA_SYNC ==> NC */
  87         PAD_NC_LOCK(GPP_R1, NONE, LOCK_CONFIG),
  88         /* R2 : HDA_SDO ==> NC */
  89         PAD_NC_LOCK(GPP_R2, NONE, LOCK_CONFIG),
  90         /* R3 : HDA_SDIO ==> NC */
  91         PAD_NC_LOCK(GPP_R3, NONE, LOCK_CONFIG),
  92         /* R4 : HDA_RST# ==> NC */
  93         PAD_NC_LOCK(GPP_R4, NONE, LOCK_CONFIG),
  94         /* R5 : HDA_SDI1 ==> NC */
  95         PAD_NC_LOCK(GPP_R5, NONE, LOCK_CONFIG),
  96         /* R6 : I2S2_TXD ==> NC */
  97         PAD_NC_LOCK(GPP_R6, NONE, LOCK_CONFIG),
  98         /* R7 : I2S2_RXD ==> NC */
  99         PAD_NC_LOCK(GPP_R7, NONE, LOCK_CONFIG),
 100 };
 101
 102 /* Early pad configuration in bootblock */
 103 static const struct pad_config early_gpio_table[] = {
 104         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 105         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 106         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 107         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 108         /* E15 : RSVD_TP ==> PCH_WP_OD */
 109         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 110         /* F11 : THC0_SPI1_CLK ==> MEM_CH_SEL */
 111         PAD_CFG_GPI(GPP_F11, NONE, DEEP),
 112         /* F14 : GSXDIN ==> EN_PP3300_SSD */
 113         PAD_CFG_GPO(GPP_F14, 1, DEEP),
 114         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 115         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 116         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 117         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 118         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 119         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 120         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 121         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 122         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 123         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 124
 125         /* CPU PCIe VGPIO for PEG60 */
 126         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 127         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 128         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 129         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 130         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 131         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 132         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 133         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 134         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 135         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 136         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 137         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 138         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 139         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 140         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 141         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 142         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 143         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 144         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 145         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 146 };
 147
 148 const struct pad_config *variant_gpio_override_table(size_t *num)
 149 {
 150         *num = ARRAY_SIZE(override_gpio_table);
 151         return override_gpio_table;
 152 }
 153
 154 const struct pad_config *variant_early_gpio_table(size_t *num)
 155 {
 156         *num = ARRAY_SIZE(early_gpio_table);
 157         return early_gpio_table;
 158 }