cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / google / brya / variants / craask / fw_config.c
blob47029ed435c8f5a76d4f2f7ba9e86a50e83b9f11
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <console/console.h>
6 #include <fw_config.h>
8 static const struct pad_config lte_disable_pads[] = {
9 /* A8 : WWAN_RF_DISABLE_ODL */
10 PAD_NC(GPP_A8, NONE),
11 /* D6 : WWAN_EN */
12 PAD_NC(GPP_D6, NONE),
13 /* F12 : WWAN_RST_L */
14 PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
15 /* H23 : WWAN_SAR_DETECT_ODL */
16 PAD_NC(GPP_H23, NONE),
19 static const struct pad_config wfc_disable_pads[] = {
20 /* D3 : WCAM_RST_L */
21 PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
22 /* D15 : EN_PP2800_WCAM_X */
23 PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
24 /* D16 : EN_PP1800_PP1200_WCAM_X */
25 PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
26 /* H22 : WCAM_MCLK_R */
27 PAD_NC(GPP_H22, NONE),
28 /* R6 : DMIC_WCAM_CLK_R */
29 PAD_NC(GPP_R6, NONE),
30 /* R7 : DMIC_WCAM_DATA */
31 PAD_NC(GPP_R7, NONE),
34 static const struct pad_config sd_disable_pads[] = {
35 /* D8 : SD_CLKREQ_ODL */
36 PAD_NC(GPP_D8, NONE),
37 /* H12 : SD_PERST_L */
38 PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
39 /* H13 : EN_PP3300_SD_X */
40 PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
43 static const struct pad_config stylus_disable_pads[] = {
44 /* F13 : SOC_PEN_DETECT_R_ODL */
45 PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
46 /* F15 : SOC_PEN_DETECT_ODL */
47 PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
50 static const struct pad_config emmc_disable_pads[] = {
51 /* I7 : EMMC_CMD */
52 PAD_NC(GPP_I7, NONE),
53 /* I8 : EMMC_D0 */
54 PAD_NC(GPP_I8, NONE),
55 /* I9 : EMMC_D1 */
56 PAD_NC(GPP_I9, NONE),
57 /* I10 : EMMC_D2 */
58 PAD_NC(GPP_I10, NONE),
59 /* I11 : EMMC_D3 */
60 PAD_NC(GPP_I11, NONE),
61 /* I12 : EMMC_D4 */
62 PAD_NC(GPP_I12, NONE),
63 /* I13 : EMMC_D5 */
64 PAD_NC(GPP_I13, NONE),
65 /* I14 : EMMC_D6 */
66 PAD_NC(GPP_I14, NONE),
67 /* I15 : EMMC_D7 */
68 PAD_NC(GPP_I15, NONE),
69 /* I16 : EMMC_RCLK */
70 PAD_NC(GPP_I16, NONE),
71 /* I17 : EMMC_CLK */
72 PAD_NC(GPP_I17, NONE),
73 /* I18 : EMMC_RST_L */
74 PAD_NC(GPP_I18, NONE),
77 static const struct pad_config nvme_disable_pads[] = {
78 /* B4 : SSD_PERST_L */
79 PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG),
80 /* D7 : SSD_CLKREQ_ODL */
81 PAD_NC(GPP_D7, NONE),
82 /* D11 : EN_PP3300_SSD */
83 PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
84 /* E17 : SSD_PLN_L */
85 PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
88 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
90 if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
91 printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n");
92 gpio_padbased_override(padbased_table, lte_disable_pads,
93 ARRAY_SIZE(lte_disable_pads));
96 if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) {
97 printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n");
98 gpio_padbased_override(padbased_table, wfc_disable_pads,
99 ARRAY_SIZE(wfc_disable_pads));
102 if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) {
103 printk(BIOS_INFO, "Disable SD card GPIO pins.\n");
104 gpio_padbased_override(padbased_table, sd_disable_pads,
105 ARRAY_SIZE(sd_disable_pads));
108 if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) {
109 printk(BIOS_INFO, "Disable Stylus GPIO pins.\n");
110 gpio_padbased_override(padbased_table, stylus_disable_pads,
111 ARRAY_SIZE(stylus_disable_pads));
114 if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
115 printk(BIOS_INFO, "Disable eMMC GPIO pins.\n");
116 gpio_padbased_override(padbased_table, emmc_disable_pads,
117 ARRAY_SIZE(emmc_disable_pads));
120 if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
121 printk(BIOS_INFO, "Disable NVMe SSD GPIO pins.\n");
122 gpio_padbased_override(padbased_table, nvme_disable_pads,
123 ARRAY_SIZE(nvme_disable_pads));