src/mainboard/google/brya/variants/kinox/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <types.h>
   6 #include <soc/gpio.h>
   7 #include <vendorcode/google/chromeos/chromeos.h>
   8
   9 /* Pad configuration in ramstage */
  10 static const struct pad_config override_gpio_table[] = {
  11         /* A14 : USB_OC1# ==> NC */
  12         PAD_NC(GPP_A14, NONE),
  13         /* A15 : USB_OC2# ==> NC */
  14         PAD_NC(GPP_A15, NONE),
  15         /* A19 : DDSP_HPD1 ==> NC */
  16         PAD_NC(GPP_A19, NONE),
  17         /* A20 : DDSP_HPD2 ==> TCP_DP1_HPD */
  18         PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
  19         /* A21 : DDPC_CTRCLK ==> NC */
  20         PAD_NC(GPP_A21, NONE),
  21         /* A22 : DDPC_CTRLDATA ==> NC */
  22         PAD_NC(GPP_A22, NONE),
  23
  24         /* B2  : VRALERT# ==> TP153 */
  25         PAD_NC(GPP_B2, NONE),
  26
  27         /* D0  : ISH_GP0 ==> NC */
  28         PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
  29         /* D1  : ISH_GP1 ==> NC */
  30         PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
  31         /* D2  : ISH_GP2 ==> NC */
  32         PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
  33         /* D3  : ISH_GP3 ==> NC */
  34         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  35         /* D6  : SRCCLKREQ1# ==> EMMC_CLKREQ_ODL */
  36         PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
  37         /* D8  : SRCCLKREQ3# ==> NC */
  38         PAD_NC(GPP_D8, NONE),
  39         /* D9  : ISH_SPI_CS# ==> NC */
  40         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  41         /* D10 : ISH_SPI_CLK ==> NC */
  42         PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG),
  43         /* D17 : UART1_RXD ==> NC */
  44         PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  45         /* D18 : UART1_TXD ==> EMMC_PE_RST_L */
  46         PAD_CFG_GPO(GPP_D18, 1, DEEP),
  47         /* D19 : I2S_MCLK1_OUT ==> I2S_MCLK_R */
  48
  49         /* E4  : SATA_DEVSLP0 ==> USB_A1_RT_RST_ODL */
  50         PAD_CFG_GPO(GPP_E4, 1, DEEP),
  51         /* E5  : SATA_DEVSLP1 ==> USB_A0_RT_RST_ODL */
  52         PAD_CFG_GPO(GPP_E5, 1, DEEP),
  53         /* E18 : DDP1_CTRLCLK ==> NC */
  54         PAD_NC(GPP_E18, NONE),
  55         /* E19 : DDP1_CTRLDATA ==> NC */
  56         PAD_NC(GPP_E19, NONE),
  57         /* E20 : DDP2_CTRLCLK ==> TCP_DP1_CTRLCLK */
  58         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
  59         /* E21 : DDP2_CTRLDATA ==> TCP_DP1_CTRLDATA */
  60         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
  61
  62
  63         /* F11 : THC1_SPI2_CLK ==> NC */
  64         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
  65         /* F12 : GSXDOUT ==> NC */
  66         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
  67         /* F13 : GSXDOUT ==> NC */
  68         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
  69         /* F15 : GSXSRESET# ==> NC */
  70         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
  71         /* F16 : GSXCLK ==> NC */
  72         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
  73
  74         /* H3  : SX_EXIT_HOLDOFF# ==> WLAN_PCIE_WAKE_ODL */
  75         PAD_CFG_GPI_SCI_LOW_LOCK(GPP_H3, NONE, EDGE_SINGLE, LOCK_CONFIG),
  76         /* H12 : I2C7_SDA ==> NC */
  77         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
  78         /* H23 : SRCCLKREQ5# ==> NC */
  79         PAD_NC(GPP_H23, NONE),
  80
  81         /* R4 : HDA_RST# ==> NC */
  82         PAD_NC(GPP_R4, NONE),
  83         /* R5 : HDA_SDI1 ==> NC */
  84         PAD_NC(GPP_R5, NONE),
  85         /* R6 : I2S2_TXD ==> NC */
  86         PAD_NC(GPP_R6, NONE),
  87         /* R7 : I2S2_RXD ==> NC */
  88         PAD_NC(GPP_R7, NONE),
  89 };
  90
  91 /* Early pad configuration in bootblock */
  92 static const struct pad_config early_gpio_table[] = {
  93         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
  94         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
  95         /* B4  : PROC_GP3 ==> SSD_PERST_L */
  96         PAD_CFG_GPO(GPP_B4, 0, DEEP),
  97         /* D18 : UART1_TXD ==> EMMC_PE_RST_L */
  98         PAD_CFG_GPO(GPP_D18, 0, DEEP),
  99         /* E15 : RSVD_TP ==> PCH_WP_OD */
 100         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 101         /* F14 : GSXDIN ==> EN_PP3300_SSD */
 102         PAD_CFG_GPO(GPP_F14, 1, DEEP),
 103         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 104         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 105         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 106         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 107         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 108         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 109         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 110         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 111         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 112         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 113         /* H13 : I2C7_SCL ==> EN_PP3300_EMMC */
 114         PAD_CFG_GPO(GPP_H13, 1, DEEP),
 115
 116         /* CPU PCIe VGPIO for PEG60 */
 117         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 118         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 119         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 120         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 121         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 122         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 123         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 124         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 125         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 126         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 127         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 128         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 129         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 130         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 131         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 132         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 133         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 134         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 135         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 136         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 137 };
 138
 139 static const struct pad_config romstage_gpio_table[] = {
 140         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 141         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 142 };
 143
 144 const struct pad_config *variant_gpio_override_table(size_t *num)
 145 {
 146         *num = ARRAY_SIZE(override_gpio_table);
 147         return override_gpio_table;
 148 }
 149
 150 const struct pad_config *variant_early_gpio_table(size_t *num)
 151 {
 152         *num = ARRAY_SIZE(early_gpio_table);
 153         return early_gpio_table;
 154 }
 155
 156 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 157 {
 158         *num = ARRAY_SIZE(romstage_gpio_table);
 159         return romstage_gpio_table;
 160 }