cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / google / brya / variants / nivviks / fw_config.c
blob8a4655bc36a4b173c19ca37b21eb28c2f9ada8f7
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 #include <baseboard/gpio.h>
4 #include <baseboard/variants.h>
5 #include <boardid.h>
6 #include <console/console.h>
7 #include <fw_config.h>
9 static const struct pad_config lte_disable_pads_nivviks[] = {
10 /* A8 : WWAN_RF_DISABLE_ODL */
11 PAD_NC(GPP_A8, NONE),
12 /* D6 : WWAN_EN */
13 PAD_NC(GPP_D6, NONE),
14 /* F12 : WWAN_RST_L */
15 PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
16 /* H19 : SOC_I2C_SUB_INT_ODL */
17 PAD_NC(GPP_H19, NONE),
18 /* H23 : WWAN_SAR_DETECT_ODL */
19 PAD_NC(GPP_H23, NONE),
22 static const struct pad_config lte_disable_pads_nirwen[] = {
23 /* A8 : WWAN_RF_DISABLE_ODL */
24 PAD_NC(GPP_A8, NONE),
25 /* E13 : WWAN_EN */
26 PAD_NC_LOCK(GPP_E13, NONE, LOCK_CONFIG),
27 /* F12 : WWAN_RST_L */
28 PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
29 /* H19 : SOC_I2C_SUB_INT_ODL */
30 PAD_NC(GPP_H19, NONE),
31 /* H23 : WWAN_SAR_DETECT_ODL */
32 PAD_NC(GPP_H23, NONE),
35 static const struct pad_config sd_disable_pads[] = {
36 /* D8 : SD_CLKREQ_ODL */
37 PAD_NC(GPP_D8, NONE),
38 /* H12 : SD_PERST_L */
39 PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
40 /* H13 : EN_PP3300_SD_X */
41 PAD_NC_LOCK(GPP_H13, NONE, LOCK_CONFIG),
44 static const struct pad_config wfc_disable_pads[] = {
45 /* D3 : WCAM_RST_L */
46 PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
47 /* D15 : EN_PP2800_WCAM_X */
48 PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
49 /* D16 : EN_PP1800_PP1200_WCAM_X */
50 PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
51 /* H22 : WCAM_MCLK_R */
52 PAD_NC(GPP_H22, NONE),
53 /* R6 : DMIC_WCAM_CLK_R */
54 PAD_NC(GPP_R6, NONE),
55 /* R7 : DMIC_WCAM_DATA */
56 PAD_NC(GPP_R7, NONE),
59 static const struct pad_config emmc_disable_pads[] = {
60 /* I7 : EMMC_CMD */
61 PAD_NC(GPP_I7, NONE),
62 /* I8 : EMMC_D0 */
63 PAD_NC(GPP_I8, NONE),
64 /* I9 : EMMC_D1 */
65 PAD_NC(GPP_I9, NONE),
66 /* I10 : EMMC_D2 */
67 PAD_NC(GPP_I10, NONE),
68 /* I11 : EMMC_D3 */
69 PAD_NC(GPP_I11, NONE),
70 /* I12 : EMMC_D4 */
71 PAD_NC(GPP_I12, NONE),
72 /* I13 : EMMC_D5 */
73 PAD_NC(GPP_I13, NONE),
74 /* I14 : EMMC_D6 */
75 PAD_NC(GPP_I14, NONE),
76 /* I15 : EMMC_D7 */
77 PAD_NC(GPP_I15, NONE),
78 /* I16 : EMMC_RCLK */
79 PAD_NC(GPP_I16, NONE),
80 /* I17 : EMMC_CLK */
81 PAD_NC(GPP_I17, NONE),
82 /* I18 : EMMC_RST_L */
83 PAD_NC(GPP_I18, NONE),
86 static const struct pad_config nvme_disable_pads[] = {
87 /* B4 : SSD_PERST_L */
88 PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG),
89 /* D6 : SSD_CLKREQ_ODL */
90 PAD_NC(GPP_D6, NONE),
91 /* D11 : EN_PP3300_SSD */
92 PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
93 /* E17 : SSD_PLN_L */
94 PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
97 static const struct pad_config stylus_disable_pads[] = {
98 /* F13 : SOC_PEN_DETECT_R_ODL */
99 PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
100 /* F15 : SOC_PEN_DETECT_ODL */
101 PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
104 void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
106 if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
107 if (board_id() >= 2) {
108 printk(BIOS_INFO, "Disable LTE-related GPIO pins on nirwen.\n");
109 gpio_padbased_override(padbased_table, lte_disable_pads_nirwen,
110 ARRAY_SIZE(lte_disable_pads_nirwen)
112 } else {
113 printk(BIOS_INFO, "Disable LTE-related GPIO pins on nivviks.\n");
114 gpio_padbased_override(padbased_table, lte_disable_pads_nivviks,
115 ARRAY_SIZE(lte_disable_pads_nivviks)
120 if (fw_config_probe(FW_CONFIG(SD_CARD, SD_ABSENT))) {
121 printk(BIOS_INFO, "Disable SD card GPIO pins.\n");
122 gpio_padbased_override(padbased_table, sd_disable_pads,
123 ARRAY_SIZE(sd_disable_pads));
126 if (fw_config_probe(FW_CONFIG(WFC, WFC_ABSENT))) {
127 printk(BIOS_INFO, "Disable MIPI WFC GPIO pins.\n");
128 gpio_padbased_override(padbased_table, wfc_disable_pads,
129 ARRAY_SIZE(wfc_disable_pads));
132 if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_EMMC))) {
133 printk(BIOS_INFO, "Disable eMMC SSD GPIO pins.\n");
134 gpio_padbased_override(padbased_table, emmc_disable_pads,
135 ARRAY_SIZE(emmc_disable_pads));
138 if (board_id() >= 2 && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
139 printk(BIOS_INFO, "Disable NVMe SSD GPIO pins.\n");
140 gpio_padbased_override(padbased_table, nvme_disable_pads,
141 ARRAY_SIZE(nvme_disable_pads));
144 if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) {
145 printk(BIOS_INFO, "Disable Stylus GPIO pins.\n");
146 gpio_padbased_override(padbased_table, stylus_disable_pads,
147 ARRAY_SIZE(stylus_disable_pads));