src/mainboard/google/brya/variants/osiris/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A6  : ESPI_ALERT1# ==> NC */
  11         PAD_NC(GPP_A6, NONE),
  12         /* A7  : SRCCLK_OE7# ==> LAN_WAKE_ODL */
  13         PAD_CFG_GPI_SCI_LOW(GPP_A7, NONE, DEEP, EDGE_SINGLE),
  14         /* A8  : SRCCLKREQ7# ==> NC */
  15         PAD_NC(GPP_A8, NONE),
  16         /* A12 : SATAXPCIE1 ==>  NC  */
  17         PAD_NC(GPP_A12, NONE),
  18         /* A15 : USB_OC2# ==> NC */
  19         PAD_NC(GPP_A15, NONE),
  20         /* A19 : DDSP_HPD1 ==> NC */
  21         PAD_NC(GPP_A19, NONE),
  22         /* A20 : DDSP_HPD2 ==> NC */
  23         PAD_NC(GPP_A20, NONE),
  24         /* A21 : DDPC_CTRCLK ==> NC */
  25         PAD_NC(GPP_A21, NONE),
  26         /* A22 : DDPC_CTRLDATA ==> NC */
  27         PAD_NC(GPP_A22, NONE),
  28
  29         /* B2  : VRALERT# ==> NC */
  30         PAD_NC(GPP_B2, NONE),
  31         /* B3  : PROC_GP2 ==> NC */
  32         PAD_NC(GPP_B3, NONE),
  33         /* B7  : ISH_12C1_SDA ==> NC */
  34         PAD_NC(GPP_B7, NONE),
  35         /* B8  : ISH_I2C1_SCL ==> NC */
  36         PAD_NC(GPP_B8, NONE),
  37         /* B15 : TIME_SYNC0 ==> NC */
  38         PAD_NC(GPP_B15, NONE),
  39
  40         /* C0  : SMBCLK ==> NC */
  41         PAD_NC(GPP_C0, NONE),
  42         /* C1  : SMBDATA ==> NC */
  43         PAD_NC(GPP_C1, NONE),
  44         /* C3 : SML0CLK ==> NC */
  45         PAD_NC(GPP_C3, NONE),
  46         /* C4 : SML0DATA ==> NC */
  47         PAD_NC(GPP_C4, NONE),
  48         /* C6  : SML1CLK ==> NC */
  49         PAD_NC(GPP_C6, NONE),
  50         /* C7  : SML1DATA ==> NC */
  51         PAD_NC(GPP_C7, NONE),
  52
  53         /* D0  : ISH_GP0 ==> NC */
  54         PAD_NC_LOCK(GPP_D0, NONE, LOCK_CONFIG),
  55         /* D1  : ISH_GP1 ==> NC */
  56         PAD_NC_LOCK(GPP_D1, NONE, LOCK_CONFIG),
  57         /* D2  : ISH_GP2 ==> NC */
  58         PAD_NC_LOCK(GPP_D2, NONE, LOCK_CONFIG),
  59         /* D3  : ISH_GP3 ==> NC */
  60         PAD_NC_LOCK(GPP_D3, NONE, LOCK_CONFIG),
  61         /* D5  : SRCCLKREQ0# ==> SSD_CLKREQ_ODL */
  62         PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
  63         /* D6  : SRCCLKREQ1# ==> NC */
  64         PAD_NC(GPP_D6, NONE),
  65         /* D7  : SRCCLKREQ2# ==> NC */
  66         PAD_NC(GPP_D7, NONE),
  67         /* D8  : SRCCLKREQ3# ==> NC */
  68         PAD_NC(GPP_D8, NONE),
  69         /* D9  : ISH_SPI_CS# ==> NC */
  70         PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG),
  71         /* D13 : ISH_UART0_RXD ==> NC */
  72         PAD_NC_LOCK(GPP_D13, NONE, LOCK_CONFIG),
  73         /* D14 : ISH_UART0_TXD ==> NC */
  74         PAD_NC_LOCK(GPP_D14, NONE, LOCK_CONFIG),
  75         /* D15 : ISH_UART0_RTS# ==> NC */
  76         PAD_NC_LOCK(GPP_D15, NONE, LOCK_CONFIG),
  77         /* D16 : ISH_UART0_CTS# ==> NC */
  78         PAD_NC_LOCK(GPP_D16, NONE, LOCK_CONFIG),
  79         /* D17 : UART1_RXD ==> NC */
  80         PAD_NC_LOCK(GPP_D17, NONE, LOCK_CONFIG),
  81         /* D18 : UART1_TXD ==> NC */
  82         PAD_NC_LOCK(GPP_D18, NONE, LOCK_CONFIG),
  83
  84         /* E0  : SATAXPCIE0 ==> NC */
  85         PAD_NC(GPP_E0, NONE),
  86         /* E3  : PROC_GP0 ==> NC */
  87         PAD_NC(GPP_E3, NONE),
  88         /* E4  : SATA_DEVSLP0 ==> NC */
  89         PAD_NC(GPP_E4, NONE),
  90         /* E7  : PROC_GP1 ==> NC */
  91         PAD_NC(GPP_E7, NONE),
  92         /* E10 : THC0_SPI1_CS# ==> NC */
  93         PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
  94         /* E16 : RSVD_TP ==> NC */
  95         PAD_NC(GPP_E16, NONE),
  96         /* E17 : THC0_SPI1_INT# ==> NC */
  97         PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
  98         /* E18 : DDP1_CTRLCLK ==> NC */
  99         PAD_NC(GPP_E18, NONE),
 100         /* E20 : DDP2_CTRLCLK ==> NC */
 101         PAD_NC(GPP_E20, NONE),
 102         /* E22 : DDPA_CTRLCLK ==> NC */
 103         PAD_NC(GPP_E22, NONE),
 104         /* E23 : DDPA_CTRLDATA ==> NC */
 105         PAD_NC(GPP_E23, NONE),
 106
 107         /* F6  : CNV_PA_BLANKING ==> NC */
 108         PAD_NC(GPP_F6, NONE),
 109         /* F11 : THC1_SPI2_CLK ==> NC */
 110         PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG),
 111         /* F12 : GSXDOUT ==> NC */
 112         PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG),
 113         /* F13 : GSXDOUT ==> NC */
 114         PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG),
 115         /* F15 : GSXSRESET# ==> NC */
 116         PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG),
 117         /* F16 : GSXCLK ==> NC */
 118         PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG),
 119         /* F19 : SRCCLKREQ6# ==> LAN_CLKREQ_ODL */
 120         PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 121         /* F20 : EXT_PWR_GATE# ==> NC */
 122         PAD_NC(GPP_F20, NONE),
 123         /* F21 : EXT_PWR_GATE2# ==> NC */
 124         PAD_NC(GPP_F21, NONE),
 125
 126         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 127         PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
 128         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 129         PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
 130         /* H8  : I2C4_SDA ==> NC */
 131         PAD_NC(GPP_H8, NONE),
 132         /* H9  : I2C4_SCL ==> NC */
 133         PAD_NC(GPP_H9, NONE),
 134         /* H12 : I2C7_SDA ==> NC */
 135         PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
 136         /* H19 : SRCCLKREQ4# ==> NC */
 137         PAD_NC(GPP_H19, NONE),
 138         /* H20 : IMGCLKOUT1 ==> NC */
 139         PAD_NC(GPP_H20, NONE),
 140         /* H21 : IMGCLKOUT2 ==> NC */
 141         PAD_NC(GPP_H21, NONE),
 142         /* H22 : IMGCLKOUT3 ==> LAN_PE_ISOLATE_ODL */
 143         PAD_CFG_GPO(GPP_H22, 1, DEEP),
 144         /* H23 : SRCCLKREQ5# ==> NC */
 145         PAD_NC(GPP_H23, NONE),
 146
 147         /* R4 : HDA_RST# ==> DMIC_CLK0_R */
 148         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
 149         /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
 150         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
 151         /* R6 : I2S2_TXD ==> DMIC_CLK1_R */
 152         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3),
 153         /* R7 : I2S2_RXD ==> DMIC_DATA1_R */
 154         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3),
 155
 156         /* S0 : SNDW0_CLK ==> I2S1_SPKR_SCLK_R */
 157         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
 158         /* S1 : SNDW0_DATA ==> I2S1_SPKR_SFRM_R */
 159         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
 160         /* S2 : SNDW1_CLK ==> I2S1_PCH_TX_SPKR_RX_R */
 161         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
 162         /* S3 : SNDW1_DATA ==> I2S1_PCH_RX_SPKR_TX */
 163         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
 164
 165         /* GPD11: LANPHYC ==> NC */
 166         PAD_NC(GPD11, NONE),
 167 };
 168
 169 /* Early pad configuration in bootblock */
 170 static const struct pad_config early_gpio_table[] = {
 171         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 172         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 173         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 174         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 175
 176         /* D11 : ISH_SPI_MISO ==> EN_PP3300_SSD */
 177         PAD_CFG_GPO(GPP_D11, 1, DEEP),
 178         /* E0  : SATAXPCIE0 ==> NC */
 179         PAD_NC(GPP_E0, NONE),
 180         /* E13 : THC0_SPI1_IO2 ==> MEM_CH_SEL */
 181         PAD_CFG_GPI(GPP_E13, NONE, DEEP),
 182         /* E15 : RSVD_TP ==> PCH_WP_OD */
 183         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 184         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 185         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 186         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 187         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 188         /* H7  : I2C1_SCL ==> PCH_I2C_TPM_SCL */
 189         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 190         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 191         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 192         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 193         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 194
 195         /* CPU PCIe VGPIO for PEG60 */
 196         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 197         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 198         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 199         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 200         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 201         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 202         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 203         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 204         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 205         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 206         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 207         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 208         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 209         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 210         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 211         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 212         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 213         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 214         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 215         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 216 };
 217
 218 static const struct pad_config romstage_gpio_table[] = {
 219         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 220         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 221 };
 222
 223 const struct pad_config *variant_gpio_override_table(size_t *num)
 224 {
 225         *num = ARRAY_SIZE(override_gpio_table);
 226         return override_gpio_table;
 227 }
 228
 229 const struct pad_config *variant_early_gpio_table(size_t *num)
 230 {
 231         *num = ARRAY_SIZE(early_gpio_table);
 232         return early_gpio_table;
 233 }
 234
 235 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 236 {
 237         *num = ARRAY_SIZE(romstage_gpio_table);
 238         return romstage_gpio_table;
 239 }