cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / google / brya / variants / skolas / fw_config.c
blob86246dbb2d9c1d04516fa9d7334281b070b5f80f
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootstate.h>
4 #include <console/console.h>
5 #include <fw_config.h>
6 #include <gpio.h>
8 static const struct pad_config dmic_enable_pads[] = {
9 PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), /* DMIC_CLK0_R */
10 PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), /* DMIC_DATA0_R */
11 PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK1_R */
12 PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA1_R */
15 static const struct pad_config dmic_disable_pads[] = {
16 PAD_NC(GPP_S2, NONE),
17 PAD_NC(GPP_S3, NONE),
18 PAD_NC(GPP_S6, NONE),
19 PAD_NC(GPP_S7, NONE),
22 static const struct pad_config sndw_enable_pads[] = {
23 PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), /* SDW_HP_CLK_R */
24 PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), /* SDW_HP_DATA_R */
25 PAD_CFG_NF(GPP_S4, NONE, DEEP, NF1), /* SDW_SPKR_CLK */
26 PAD_CFG_NF(GPP_S5, NONE, DEEP, NF1), /* SDW_SPKR_DATA */
29 static const struct pad_config max98360_enable_pads[] = {
30 PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4), /* I2S_SPKR_SCLK_R */
31 PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4), /* I2S_SPKR_SFRM_R */
32 PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4), /* I2S_PCH_TX_SPKR_RX_R */
33 PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4), /* I2S_PCH_RX_SPKR_TX */
34 PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), /* DMIC_CLK0_R */
35 PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), /* DMIC_DATA0_R */
36 PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3), /* DMIC_CLK1_R */
37 PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3), /* DMIC_DATA1_R */
38 PAD_NC(GPP_R6, NONE),
39 PAD_NC(GPP_R7, NONE),
42 static const struct pad_config nau8318_enable_pads[] = {
43 PAD_CFG_GPO(GPP_R7, 0, DEEP), /* SPK_BEEP_EN */
46 static const struct pad_config sndw_disable_pads[] = {
47 PAD_NC(GPP_S0, NONE),
48 PAD_NC(GPP_S1, NONE),
49 PAD_NC(GPP_S4, NONE),
50 PAD_NC(GPP_S5, NONE),
53 static const struct pad_config i2s0_enable_pads[] = {
54 PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), /* I2S_HP_SCLK_R */
55 PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), /* I2S_HP_SFRM_R */
56 PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), /* I2S_PCH_TX_HP_RX_STRAP */
57 PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), /* I2S_PCH_RX_HP_TX */
60 static const struct pad_config i2s2_enable_pads[] = {
61 PAD_CFG_NF(GPP_R4, NONE, DEEP, NF2), /* I2S_SPKR_SCLK_R */
62 PAD_CFG_NF(GPP_R5, NONE, DEEP, NF2), /* I2S_SPKR_SFRM_R */
63 PAD_CFG_NF(GPP_R6, NONE, DEEP, NF2), /* I2S_PCH_TX_SPKR_RX_R */
64 PAD_CFG_NF(GPP_R7, NONE, DEEP, NF2), /* I2S_PCH_RX_SPKR_TX */
67 static const struct pad_config i2s0_disable_pads[] = {
68 PAD_NC(GPP_R0, NONE),
69 PAD_NC(GPP_R1, NONE),
70 PAD_NC(GPP_R2, NONE),
71 PAD_NC(GPP_R3, NONE),
74 static const struct pad_config i2s2_disable_pads[] = {
75 PAD_NC(GPP_R4, NONE),
76 PAD_NC(GPP_R5, NONE),
77 PAD_NC(GPP_R6, NONE),
78 PAD_NC(GPP_R7, NONE),
81 static const struct pad_config bt_i2s_enable_pads[] = {
82 PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF3), /* BT_I2S_BCLK */
83 PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF3), /* BT_I2S_SYNC */
84 PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF3), /* BT_I2S_SDO */
85 PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF3), /* BT_I2S_SDI */
86 PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), /* SSP2_SCLK */
87 PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), /* SSP2_SFRM */
88 PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), /* SSP_TXD */
89 PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), /* SSP_RXD */
92 static const struct pad_config bt_i2s_disable_pads[] = {
93 PAD_NC(GPP_VGPIO_30, NONE),
94 PAD_NC(GPP_VGPIO_31, NONE),
95 PAD_NC(GPP_VGPIO_32, NONE),
96 PAD_NC(GPP_VGPIO_33, NONE),
97 PAD_NC(GPP_VGPIO_34, NONE),
98 PAD_NC(GPP_VGPIO_35, NONE),
99 PAD_NC(GPP_VGPIO_36, NONE),
100 PAD_NC(GPP_VGPIO_37, NONE),
103 static const struct pad_config hps_disable_pads[] = {
104 /* E3 : PROC_GP0 ==> HPS_INT_ODL */
105 PAD_NC(GPP_E3, NONE),
106 /* E7 : PROC_GP1 ==> EN_HPS_PWR */
107 PAD_NC(GPP_E7, NONE),
108 /* F20 : EXT_PWR_GATE# ==> HPS_RST_R */
109 PAD_NC(GPP_F20, NONE),
112 static const struct pad_config lte_disable_pads[] = {
113 /* A7 : WWAN_PCIE_WAKE_ODL */
114 PAD_NC(GPP_A7, NONE),
115 /* A8 : WWAN_RF_DISABLE_ODL */
116 PAD_NC(GPP_A8, NONE),
117 /* D5 : SRCCLKREQ0# ==> WWAN_DPR_SAR_ODL */
118 PAD_NC(GPP_D5, NONE),
119 /* E0 : SATAXPCIE0 ==> WWAN_PERST_L */
120 PAD_NC(GPP_E0, NONE),
121 /* E10 : THC0_SPI1_CS# ==> WWAN_CONFIG0 */
122 PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG),
123 /* E16 : WWAN_RST_L */
124 PAD_NC(GPP_E16, NONE),
125 /* E17 : THC0_SPI1_INT# ==> WWAN_CONFIG3 */
126 PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
127 /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L */
128 PAD_NC(GPP_F21, NONE),
129 /* H23 : SRCCLKREQ5# ==> WWAN_CLKREQ_ODL */
130 PAD_NC(GPP_H23, NONE),
131 /* GPD11 : LANPHYC ==> WWAN_CONFIG1 */
132 PAD_NC(GPD11, NONE),
135 static void enable_i2s(void)
137 gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
138 gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
139 gpio_configure_pads(i2s2_enable_pads, ARRAY_SIZE(i2s2_enable_pads));
140 gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
143 static void fw_config_handle(void *unused)
145 if (!fw_config_is_provisioned() || fw_config_probe(FW_CONFIG(AUDIO, AUDIO_UNKNOWN))) {
146 printk(BIOS_INFO, "Disable audio related GPIO pins.\n");
147 gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
148 gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
149 gpio_configure_pads(dmic_disable_pads, ARRAY_SIZE(dmic_disable_pads));
150 gpio_configure_pads(sndw_disable_pads, ARRAY_SIZE(sndw_disable_pads));
151 return;
154 if (fw_config_probe(FW_CONFIG(AUDIO, MAX98373_ALC5682_SNDW))) {
155 printk(BIOS_INFO, "Configure audio over SoundWire with MAX98373 ALC5682.\n");
156 gpio_configure_pads(dmic_enable_pads, ARRAY_SIZE(dmic_enable_pads));
157 gpio_configure_pads(sndw_enable_pads, ARRAY_SIZE(sndw_enable_pads));
158 printk(BIOS_INFO, "BT offload enabled\n");
159 gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
160 gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
161 gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
162 } else if (!fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S))) {
163 printk(BIOS_INFO, "BT offload disabled\n");
164 gpio_configure_pads(i2s0_disable_pads, ARRAY_SIZE(i2s0_disable_pads));
165 gpio_configure_pads(i2s2_disable_pads, ARRAY_SIZE(i2s2_disable_pads));
166 gpio_configure_pads(bt_i2s_disable_pads, ARRAY_SIZE(bt_i2s_disable_pads));
169 if (fw_config_probe(FW_CONFIG(AUDIO, MAX98357_ALC5682I_I2S))) {
170 printk(BIOS_INFO, "Configure audio over I2S with MAX98357 ALC5682I.\n");
171 enable_i2s();
174 if (fw_config_probe(FW_CONFIG(AUDIO, ALC1019_NAU88L25B_I2S))) {
175 printk(BIOS_INFO, "Configure audio over I2S with ALC1019 NAU88L25B.\n");
176 enable_i2s();
179 if (fw_config_probe(FW_CONFIG(AUDIO, MAX98360_ALC5682I_I2S)) ||
180 fw_config_probe(FW_CONFIG(AUDIO, NAU8318_NAU88L25B_I2S))) {
181 printk(BIOS_INFO, "Configure audio over I2S with MAX98360 ALC5682I.\n");
182 gpio_configure_pads(max98360_enable_pads, ARRAY_SIZE(max98360_enable_pads));
183 printk(BIOS_INFO, "BT offload enabled\n");
184 gpio_configure_pads(i2s0_enable_pads, ARRAY_SIZE(i2s0_enable_pads));
185 gpio_configure_pads(bt_i2s_enable_pads, ARRAY_SIZE(bt_i2s_enable_pads));
187 if (fw_config_probe(FW_CONFIG(AUDIO, NAU8318_NAU88L25B_I2S)))
188 gpio_configure_pads(nau8318_enable_pads, ARRAY_SIZE(nau8318_enable_pads));
191 if (fw_config_probe(FW_CONFIG(DB_LTE, LTE_ABSENT))) {
192 printk(BIOS_INFO, "Disable LTE related GPIO pins.\n");
193 gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads));
196 if (fw_config_probe(FW_CONFIG(HPS, HPS_ABSENT))) {
197 printk(BIOS_INFO, "Disable HPS related GPIO pins.\n");
198 gpio_configure_pads(hps_disable_pads, ARRAY_SIZE(hps_disable_pads));
201 BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL);