src/mainboard/google/brya/variants/vell/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6 #include <soc/gpio.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config override_gpio_table[] = {
  10         /* A11 : PMC_I2C_SDA ==> NC */
  11         PAD_NC(GPP_A11, NONE),
  12
  13         /* B2  : VRALERT# ==> RGB_RST_ODL */
  14         PAD_NC(GPP_B2, NONE),
  15         /* B15  : TIME_SYNC0 ==> NC */
  16         PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG),
  17
  18         /* C3 : SML0CLK ==> NC */
  19         PAD_NC(GPP_C3, NONE),
  20
  21         /* D3  : ISH_GP3 ==> EN_PP3300_SSD */
  22         PAD_CFG_GPO_LOCK(GPP_D3, 1, LOCK_CONFIG),
  23         /* D11 : ISH_SPI_MISO ==> USB_C3_LSX_TX */
  24         PAD_CFG_NF_LOCK(GPP_D11, NONE, NF4, LOCK_CONFIG),
  25         /* D12 : ISH_SPI_MOSI ==> USB_C3_LSX_RX_STRAP */
  26         PAD_CFG_NF_LOCK(GPP_D12, NONE, NF4, LOCK_CONFIG),
  27
  28         /* E3  : PROC_GP0 ==> MEM_STRAP_0 */
  29         PAD_CFG_GPI(GPP_E3, NONE, DEEP),
  30         /* E5  : SATA_DEVSLP1 ==> MEM_CH_SEL */
  31         PAD_CFG_GPI(GPP_E5, NONE, DEEP),
  32         /* E7  : PROC_GP1 ==> MEM_STRAP_3 */
  33         PAD_CFG_GPI(GPP_E7, NONE, DEEP),
  34         /* E10 : THC0_SPI1_CS# ==> UWB_GSPI0_CS */
  35         PAD_CFG_NF_LOCK(GPP_E10, NONE, NF2, LOCK_CONFIG),
  36         /* E11 : THC0_SPI1_CLK ==> UWB_CLK */
  37         PAD_CFG_NF_LOCK(GPP_E11, NONE, NF2, LOCK_CONFIG),
  38         /* E12 : THC0_SPI1_IO1 ==> UWB_GSPI0_DI */
  39         PAD_CFG_NF_LOCK(GPP_E12, NONE, NF3, LOCK_CONFIG),
  40         /* E13 : THC0_SPI1_IO2 ==> UWB_GSPI0_DO */
  41         PAD_CFG_NF_LOCK(GPP_E13, NONE, NF3, LOCK_CONFIG),
  42         /* E16 : RSVD_TP ==> WWAN_RST_L */
  43         PAD_CFG_GPO(GPP_E16, 1, DEEP),
  44         /* E22 : DDPA_CTRLCLK ==> WWAN_CONFIG0 */
  45         PAD_CFG_GPI(GPP_E22, NONE, DEEP),
  46         /* E23 : DDPA_CTRLDATA ==> USB_C3_OC_ODL */
  47         PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
  48         /*
  49          * E0 : SATAXPCIE0 ==> WWAN_PERST_L
  50          * Drive high here, so that PERST_L is sequenced after RST_L
  51          */
  52         PAD_CFG_GPO(GPP_E0, 1, DEEP),
  53         /* F19 : NC */
  54         PAD_NC(GPP_F19, NONE),
  55
  56         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
  57         PAD_CFG_NF_LOCK(GPP_H6, NONE, NF1, LOCK_CONFIG),
  58         /* H7  : IC1_SCL ==> PCH_I2C_TPM_SCL */
  59         PAD_CFG_NF_LOCK(GPP_H7, NONE, NF1, LOCK_CONFIG),
  60         /* H12 : I2C7_SDA ==> PCH_I2C_AUD_L_SDA */
  61         PAD_CFG_NF_LOCK(GPP_H12, NONE, NF1, LOCK_CONFIG),
  62         /* H13 : I2C7_SCL ==> PCH_I2C_AUD_L_SCL */
  63         PAD_CFG_NF_LOCK(GPP_H13, NONE, NF1, LOCK_CONFIG),
  64         /* H15 : DDPB_CTRLCLK ==> USB_C3_AUX_DC_P */
  65         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF6),
  66         /* H17 : DDPB_CTRLDATA ==> USB_C3_AUX_DC_N */
  67         PAD_CFG_NF(GPP_H17, NONE, DEEP, NF6),
  68         /* H21 : IMGCLKOUT2 ==>  UCAM_MCLK_R */
  69         PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1),
  70
  71         /* R4 : HDA_RST# ==> DMIC_CLK0_R */
  72         PAD_CFG_NF(GPP_R4, NONE, DEEP, NF3),
  73         /* R5 : HDA_SDI1 ==> DMIC_DATA0_R */
  74         PAD_CFG_NF(GPP_R5, NONE, DEEP, NF3),
  75         /* R6 : NC */
  76         PAD_NC(GPP_R6, NONE),
  77         /* R7 : NC */
  78         PAD_NC(GPP_R7, NONE),
  79
  80         /* S0 : SNDW0_CLK ==> I2S_SPKR_SCLK_R */
  81         PAD_CFG_NF(GPP_S0, NONE, DEEP, NF4),
  82         /* S1 : SNDW0_DATA ==> I2S_SPKR_SFRM_R */
  83         PAD_CFG_NF(GPP_S1, NONE, DEEP, NF4),
  84         /* S2 : SNDW1_CLK ==> DMIC_CLK0_R */
  85         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF4),
  86         /* S3 : SNDW1_DATA ==> I2S_PCH_RX_SPKR_TX */
  87         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF4),
  88         /* S4 : SNDW2_CLK ==> NC */
  89         PAD_NC(GPP_S4, NONE),
  90         /* S5 : SNDW2_DATA ==> NC */
  91         PAD_NC(GPP_S5, NONE),
  92         /* S6 : SNDW3_CLK ==> NC */
  93         PAD_NC(GPP_S6, NONE),
  94         /* S7 : SNDW3_DATA ==> NC */
  95         PAD_NC(GPP_S7, NONE),
  96
  97         /* GPD11: LANPHYC ==> WWAN_CONFIG1 */
  98         PAD_NC(GPD11, NONE),
  99 };
 100
 101 /* Early pad configuration in bootblock */
 102 static const struct pad_config early_gpio_table[] = {
 103         /* A12 : SATAXPCIE1 ==> EN_PP3300_WWAN */
 104         PAD_CFG_GPO(GPP_A12, 1, DEEP),
 105         /* A13 : PMC_I2C_SCL ==> GSC_PCH_INT_ODL */
 106         PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT),
 107         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 108         PAD_CFG_GPO(GPP_B4, 0, DEEP),
 109         /* H6  : I2C1_SDA ==> PCH_I2C_TPM_SDA */
 110         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 111         /* H7  : IC1_SCL ==> PCH_I2C_TPM_SCL */
 112         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 113         /*
 114          * D1  : ISH_GP1 ==> FP_RST_ODL
 115          * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down.
 116          * To ensure proper power sequencing for the FPMCU device, reset signal is driven low
 117          * early on in bootblock, followed by enabling of power. Reset signal is deasserted
 118          * later on in ramstage. Since reset signal is asserted in bootblock, it results in
 119          * FPMCU not working after a S3 resume. This is a known issue.
 120          */
 121         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 122         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 123         PAD_CFG_GPO(GPP_D2, 1, DEEP),
 124         /* D3  : ISH_GP3 ==> EN_PP3300_SSD */
 125         PAD_CFG_GPO(GPP_D3, 1, DEEP),
 126         /* D11 : ISH_SPI_MISO ==> USB_C0_LSX_SOC_TX */
 127         PAD_CFG_NF(GPP_D11, NONE, DEEP, NF4),
 128         /* E0  : SATAXPCIE0 ==> WWAN_PERST_L (updated in ramstage) */
 129         PAD_CFG_GPO(GPP_E0, 0, DEEP),
 130         /* E3  : PROC_GP0 ==> MEM_STRAP_0 */
 131         PAD_CFG_GPI(GPP_E3, NONE, DEEP),
 132         /* E5  : SATA_DEVSLP1 ==> MEM_CH_SEL */
 133         PAD_CFG_GPI(GPP_E5, NONE, DEEP),
 134         /* E7  : PROC_GP1 ==> MEM_STRAP_3 */
 135         PAD_CFG_GPI(GPP_E7, NONE, DEEP),
 136
 137         /* E15 : RSVD_TP ==> PCH_WP_OD */
 138         PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
 139         /* E16 : RSVD_TP ==> WWAN_RST_L  */
 140         PAD_CFG_GPO(GPP_E16, 0, DEEP),
 141         /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */
 142         PAD_CFG_GPI(GPP_F18, NONE, DEEP),
 143         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (updated in romstage) */
 144         PAD_CFG_GPO(GPP_F21, 0, DEEP),
 145         /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */
 146         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2),
 147         /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */
 148         PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2),
 149
 150         /*Add virtual GPIOs for CPU PCIe RP*/
 151         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_48, NONE, PLTRST, NF1),
 152         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_49, NONE, PLTRST, NF1),
 153         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_50, NONE, PLTRST, NF1),
 154         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_51, NONE, PLTRST, NF1),
 155         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_52, NONE, PLTRST, NF1),
 156         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_53, NONE, PLTRST, NF1),
 157         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_54, NONE, PLTRST, NF1),
 158         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_55, NONE, PLTRST, NF1),
 159         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_56, NONE, PLTRST, NF1),
 160         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_57, NONE, PLTRST, NF1),
 161         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_58, NONE, PLTRST, NF1),
 162         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_59, NONE, PLTRST, NF1),
 163         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_60, NONE, PLTRST, NF1),
 164         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_61, NONE, PLTRST, NF1),
 165         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_62, NONE, PLTRST, NF1),
 166         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_63, NONE, PLTRST, NF1),
 167         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_76, NONE, PLTRST, NF1),
 168         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_77, NONE, PLTRST, NF1),
 169         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_78, NONE, PLTRST, NF1),
 170         PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_79, NONE, PLTRST, NF1),
 171 };
 172
 173 static const struct pad_config romstage_gpio_table[] = {
 174         /* B4  : PROC_GP3 ==> SSD_PERST_L */
 175         PAD_CFG_GPO(GPP_B4, 1, DEEP),
 176         /* F21 : EXT_PWR_GATE2# ==> WWAN_FCPO_L (set here for correct power sequencing) */
 177         PAD_CFG_GPO(GPP_F21, 1, DEEP),
 178
 179         /* Enable touchscreen, hold in reset */
 180         /* C0  : SMBCLK ==> EN_PP3300_TCHSCR */
 181         PAD_CFG_GPO(GPP_C0, 1, DEEP),
 182         /* C1  : SMBDATA ==> USI_RST_L */
 183         PAD_CFG_GPO(GPP_C1, 0, DEEP),
 184
 185         /* D1  : ISH_GP1 ==> FP_RST_ODL */
 186         PAD_CFG_GPO(GPP_D1, 0, DEEP),
 187         /* D2  : ISH_GP2 ==> EN_FP_PWR */
 188         PAD_CFG_GPO(GPP_D2, 0, DEEP),
 189 };
 190
 191 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 192 {
 193         *num = ARRAY_SIZE(romstage_gpio_table);
 194         return romstage_gpio_table;
 195 }
 196
 197 const struct pad_config *variant_gpio_override_table(size_t *num)
 198 {
 199         *num = ARRAY_SIZE(override_gpio_table);
 200         return override_gpio_table;
 201 }
 202
 203 const struct pad_config *variant_early_gpio_table(size_t *num)
 204 {
 205         *num = ARRAY_SIZE(early_gpio_table);
 206         return early_gpio_table;
 207 }