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cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / google / dedede / variants / taranza / overridetree.cb
blob2b09088eef101c5888faace5936bff914bf32601
1 chip soc/intel/jasperlake
2
3 # Intel Common SoC Config
4 #+-------------------+---------------------------+
5 #| Field | Value |
6 #+-------------------+---------------------------+
7 #| GSPI0 | cr50 TPM. Early init is |
8 #| | required to set up a BAR |
9 #| | for TPM communication |
10 #| | before memory is up |
11 #| I2C4 | Audio |
12 #+-------------------+---------------------------+
13 register "common_soc_config" = "{
14 .gspi[0] = {
15 .speed_mhz = 1,
16 .early_init = 1,
17 },
18 .i2c[4] = {
19 .speed_config[0] = {
20 .speed = I2C_SPEED_FAST,
21 .scl_lcnt = 190,
22 .scl_hcnt = 100,
23 .sda_hold = 40,
24 }
25 },
26 }"
27
28 # Power limit config
29 register "power_limits_config[JSL_N4500_6W_CORE]" = "{
30 .tdp_pl1_override = 6,
31 .tdp_pl2_override = 20,
32 .tdp_pl4 = 60,
33 }"
34
35 register "power_limits_config[JSL_N5100_6W_CORE]" = "{
36 .tdp_pl1_override = 6,
37 .tdp_pl2_override = 20,
38 .tdp_pl4 = 60,
39 }"
40
41 # Enable Root Port 3 (index 2) for LAN
42 # External PCIe port 7 is mapped to PCIe Root Port 3
43 register "PcieRpEnable[2]" = "1"
44 register "PcieClkSrcUsage[4]" = "2"
45
46 # Enable Root Port 7 (index 6) for WLAN
47 # External PCIe port 3 is mapped to PCIe Root Port 7
48 register "PcieRpEnable[6]" = "1"
49 register "PcieClkSrcUsage[3]" = "6"
50
51 # Disable PCIe Root Port 8
52 register "PcieRpEnable[7]" = "0"
53
54 # Audio related configurations
55 register "PchHdaAudioLinkDmicEnable[0]" = "0"
56 register "PchHdaAudioLinkDmicEnable[1]" = "0"
57
58 # Disable SD card
59 register "sdcard_cd_gpio" = "0"
60 register "SdCardPowerEnableActiveHigh" = "0"
61
62 # Disable eDP on port A
63 register "DdiPortAConfig" = "0"
64
65 # Enable HPD and DDC for DDI port A
66 register "DdiPortAHpd" = "1"
67 register "DdiPortADdc" = "1"
68
69 # Does not support external vnn power rail
70 register "disable_external_bypass_vr" = "1"
71
72 # USB Port Configuration
73 register "usb2_ports[0]" = "{
74 .enable = 1,
75 .ocpin = OC_SKIP,
76 .tx_bias = USB2_BIAS_0MV,
77 .tx_emp_enable = USB2_PRE_EMP_ON,
78 .pre_emp_bias = USB2_BIAS_11P25MV,
79 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
80 }" # Type-C Port 0
81 register "usb2_ports[1]" = "{
82 .enable = 1,
83 .ocpin = OC1,
84 .tx_bias = USB2_BIAS_0MV,
85 .tx_emp_enable = USB2_PRE_EMP_ON,
86 .pre_emp_bias = USB2_BIAS_11P25MV,
87 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
88 }" # Type-A Port A0
89 register "usb2_ports[2]" = "{
90 .enable = 1,
91 .ocpin = OC2,
92 .tx_bias = USB2_BIAS_0MV,
93 .tx_emp_enable = USB2_PRE_EMP_ON,
94 .pre_emp_bias = USB2_BIAS_11P25MV,
95 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
96 }" # Type-A Port A1
97 register "usb2_ports[3]" = "{
98 .enable = 1,
99 .ocpin = OC3,
100 .tx_bias = USB2_BIAS_0MV,
101 .tx_emp_enable = USB2_PRE_EMP_ON,
102 .pre_emp_bias = USB2_BIAS_11P25MV,
103 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
104 }" # Type-A Port A2
105 register "usb2_ports[4]" = "{
106 .enable = 1,
107 .ocpin = OC0,
108 .tx_bias = USB2_BIAS_0MV,
109 .tx_emp_enable = USB2_PRE_EMP_ON,
110 .pre_emp_bias = USB2_BIAS_11P25MV,
111 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
112 }" # Type-A Port A3
113 register "usb2_ports[6]" = "{
114 .enable = 1,
115 .ocpin = OC_SKIP,
116 .tx_bias = USB2_BIAS_0MV,
117 .tx_emp_enable = USB2_PRE_EMP_ON,
118 .pre_emp_bias = USB2_BIAS_11P25MV,
119 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
120 }" # Type-A Port A4
121
122 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A4
123 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A2
124 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A3
125
126 # Bitmap for Wake Enable on USB attach/detach
127 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
128 USB_PORT_WAKE_ENABLE(2) |
129 USB_PORT_WAKE_ENABLE(3) |
130 USB_PORT_WAKE_ENABLE(4) |
131 USB_PORT_WAKE_ENABLE(5) |
132 USB_PORT_WAKE_ENABLE(7)"
133 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
134 USB_PORT_WAKE_ENABLE(2) |
135 USB_PORT_WAKE_ENABLE(3) |
136 USB_PORT_WAKE_ENABLE(4) |
137 USB_PORT_WAKE_ENABLE(5) |
138 USB_PORT_WAKE_ENABLE(6)"
139
140 device domain 0 on
141 device pci 04.0 on
142 chip drivers/intel/dptf
143 ## Passive Policy
144 register "policies.passive" = "{
145 [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
146 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
147 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 75, 15000),
148 [3] = DPTF_PASSIVE(CPU, TEMP_SENSOR_2, 55, 15000)
149 }"
150
151 ## Critical Policy
152 register "policies.critical" = "{
153 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
154 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
155 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
156 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 80, SHUTDOWN)
157 }"
158
159 register "controls.power_limits" = "{
160 .pl1 = {
161 .min_power = 3000,
162 .max_power = 6000,
163 .time_window_min = 1 * MSECS_PER_SEC,
164 .time_window_max = 1 * MSECS_PER_SEC,
165 .granularity = 100,
166 },
167 .pl2 = {
168 .min_power = 20000,
169 .max_power = 20000,
170 .time_window_min = 1 * MSECS_PER_SEC,
171 .time_window_max = 1 * MSECS_PER_SEC,
172 .granularity = 1000,
173 }
174 }"
175
176 register "options.tsr[0].desc" = ""Memory""
177 register "options.tsr[1].desc" = ""Power""
178 register "options.tsr[2].desc" = ""Chassis""
179
180 ## Charger Performance Control (Control, mA)
181 register "controls.charger_perf" = "{
182 [0] = { 255, 3000 },
183 [1] = { 24, 1500 },
184 [2] = { 16, 1000 },
185 [3] = { 8, 500 }
186 }"
187
188 device generic 0 on end
189 end
190 end # SA Thermal device
191 device pci 14.0 on
192 chip drivers/usb/acpi
193 device usb 0.0 on
194 chip drivers/usb/acpi
195 register "desc" = ""USB2 Type-C Port C0""
196 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
197 register "group" = "ACPI_PLD_GROUP(2, 1)"
198 device usb 2.0 on end
199 end
200 chip drivers/usb/acpi
201 register "desc" = ""USB2 Type-A Port A0""
202 register "type" = "UPC_TYPE_A"
203 register "group" = "ACPI_PLD_GROUP(2, 2)"
204 device usb 2.1 on end
205 end
206 chip drivers/usb/acpi
207 register "desc" = ""USB2 Type-A Port A1""
208 register "type" = "UPC_TYPE_A"
209 register "group" = "ACPI_PLD_GROUP(2, 3)"
210 device usb 2.2 on end
211 end
212 chip drivers/usb/acpi
213 register "desc" = ""USB2 Type-A Port A2""
214 register "type" = "UPC_TYPE_A"
215 register "group" = "ACPI_PLD_GROUP(1, 3)"
216 device usb 2.3 on end
217 end
218 chip drivers/usb/acpi
219 register "desc" = ""USB2 Type-A Port A3""
220 register "type" = "UPC_TYPE_A"
221 register "group" = "ACPI_PLD_GROUP(1, 2)"
222 device usb 2.4 on end
223 end
224 chip drivers/usb/acpi
225 register "desc" = ""USB2 Type-A Port A4""
226 register "type" = "UPC_TYPE_A"
227 register "group" = "ACPI_PLD_GROUP(1, 1)"
228 device usb 2.6 on end
229 end
230 chip drivers/usb/acpi
231 register "desc" = ""USB3 Type-C Port C0""
232 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
233 register "group" = "ACPI_PLD_GROUP(2, 1)"
234 device usb 3.0 on end
235 end
236 chip drivers/usb/acpi
237 register "desc" = ""USB3 Type-A Port A4""
238 register "type" = "UPC_TYPE_USB3_A"
239 register "group" = "ACPI_PLD_GROUP(1, 1)"
240 device usb 3.1 on end
241 end
242 chip drivers/usb/acpi
243 register "desc" = ""USB3 Type-A Port A0""
244 register "type" = "UPC_TYPE_USB3_A"
245 register "group" = "ACPI_PLD_GROUP(2, 2)"
246 device usb 3.2 on end
247 end
248 chip drivers/usb/acpi
249 register "desc" = ""USB3 Type-A Port A1""
250 register "type" = "UPC_TYPE_USB3_A"
251 register "group" = "ACPI_PLD_GROUP(2, 3)"
252 device usb 3.3 on end
253 end
254 chip drivers/usb/acpi
255 register "desc" = ""USB3 Type-A Port A3""
256 register "type" = "UPC_TYPE_USB3_A"
257 register "group" = "ACPI_PLD_GROUP(1, 2)"
258 device usb 3.4 on end
259 end
260 chip drivers/usb/acpi
261 register "desc" = ""USB3 Type-A Port A2""
262 register "type" = "UPC_TYPE_USB3_A"
263 register "group" = "ACPI_PLD_GROUP(1, 3)"
264 device usb 3.5 on end
265 end
266 end
267 end
268 end # USB xHCI
269 device pci 15.0 off end # I2C 0
270 device pci 15.1 off end # I2C 1
271 device pci 15.2 off end # I2C 2
272 device pci 15.3 off end # I2C 3
273 device pci 19.0 on
274 chip drivers/i2c/generic
275 register "hid" = ""RTL5682""
276 register "name" = ""RT58""
277 register "desc" = ""Realtek RT5682""
278 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_D16)"
279 register "property_count" = "1"
280 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
281 register "property_list[0].name" = ""realtek,jd-src""
282 register "property_list[0].integer" = "1"
283 device i2c 1a on end
284 end
285 end # I2C 4
286 device pci 1c.2 on
287 chip drivers/net
288 register "customized_leds" = "0x05af"
289 register "wake" = "GPE0_DW0_03" # GPP_B3
290 register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D4)"
291 register "device_index" = "0"
292 device pci 00.0 on end
293 end
294 end # PCI Express Root Port 3 - RTL8111H LAN
295 device pci 1c.6 on
296 chip drivers/wifi/generic
297 register "wake" = "GPE0_DW2_03"
298 device pci 00.0 on end
299 end
300 end # PCI Express Root Port 7 - WLAN
301 device pci 1c.7 off end # PCI Express Root Port 8
302 device pci 1f.3 on end # Intel HDA
303 end
304 end
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