src/mainboard/google/parrot/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <northbridge/intel/sandybridge/sandybridge.h>
   4 #include <northbridge/intel/sandybridge/raminit.h>
   5 #include <southbridge/intel/bd82x6x/pch.h>
   6 #include "ec/compal/ene932/ec.h"
   7
   8 void mainboard_late_rcba_config(void)
   9 {
  10         /*
  11          *             GFX    INTA -> PIRQA (MSI)
  12          * D28IP_P2IP  WLAN   INTA -> PIRQB
  13          * D28IP_P3IP  ETH0   INTC -> PIRQD
  14          * D29IP_E1P   EHCI1  INTA -> PIRQE
  15          * D26IP_E2P   EHCI2  INTA -> PIRQE
  16          * D31IP_SIP   SATA   INTA -> PIRQF (MSI)
  17          * D31IP_SMIP  SMBUS  INTB -> PIRQG
  18          * D31IP_TTIP  THRT   INTC -> PIRQH
  19          * D27IP_ZIP   HDA    INTA -> PIRQG (MSI)
  20          *
  21          * Trackpad DVT PIRQA (16)
  22          * Trackpad DVT PIRQE (20)
  23          */
  24
  25         /* Device interrupt pin register (board specific) */
  26         RCBA32(D31IP) = (INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  27                 (INTB << D31IP_SMIP) | (INTA << D31IP_SIP);
  28         RCBA32(D30IP) = (NOINT << D30IP_PIP);
  29         RCBA32(D29IP) = (INTA << D29IP_E1P);
  30         RCBA32(D28IP) = (NOINT << D28IP_P1IP) | (INTA << D28IP_P2IP) |
  31                 (INTC << D28IP_P3IP) | (NOINT << D28IP_P4IP) |
  32                 (NOINT << D28IP_P5IP) | (NOINT << D28IP_P6IP) |
  33                 (NOINT << D28IP_P7IP) | (NOINT << D28IP_P8IP);
  34         RCBA32(D27IP) = (INTA << D27IP_ZIP);
  35         RCBA32(D26IP) = (INTA << D26IP_E2P);
  36         RCBA32(D25IP) = (NOINT << D25IP_LIP);
  37         RCBA32(D22IP) = (NOINT << D22IP_MEI1IP);
  38
  39         /* Device interrupt route registers */
  40         DIR_ROUTE(D31IR, PIRQB, PIRQH, PIRQA, PIRQC);
  41         DIR_ROUTE(D29IR, PIRQD, PIRQE, PIRQF, PIRQG);
  42         DIR_ROUTE(D28IR, PIRQB, PIRQC, PIRQD, PIRQE);
  43         DIR_ROUTE(D27IR, PIRQA, PIRQH, PIRQA, PIRQB);
  44         DIR_ROUTE(D26IR, PIRQF, PIRQE, PIRQG, PIRQH);
  45         DIR_ROUTE(D25IR, PIRQA, PIRQB, PIRQC, PIRQD);
  46         DIR_ROUTE(D22IR, PIRQA, PIRQB, PIRQC, PIRQD);
  47 }
  48
  49 void mainboard_fill_pei_data(struct pei_data *pei_data)
  50 {
  51         /* TODO: Confirm if nortbridge_fill_pei_data() gets .system_type right (should be 0) */
  52 }
  53
  54 const struct southbridge_usb_port mainboard_usb_ports[] = {
  55         /* enabled power  USB oc pin  */
  56         { 0, 0, -1 }, /* P0: Empty */
  57         { 1, 0, 0 }, /* P1: Left USB 1  (OC0) */
  58         { 1, 0, 1 }, /* P2: Left USB 2  (OC1) */
  59         { 1, 0, 1 }, /* P3: Left USB 3  (OC1) */
  60         { 0, 0, -1 }, /* P4: Empty */
  61         { 0, 0, -1 }, /* P5: Empty */
  62         { 0, 0, -1 }, /* P6: Empty */
  63         { 0, 0, -1 }, /* P7: Empty */
  64         /* Empty and onboard Ports 8-13, set to un-used pin OC4 */
  65         { 1, 0, -1 }, /* P8: MiniPCIe (WLAN) (no OC) */
  66         { 0, 0, -1 }, /* P9: Empty */
  67         { 1, 0, -1 }, /* P10: Camera (no OC) */
  68         { 0, 0, -1 }, /* P11: Empty */
  69         { 0, 0, -1 }, /* P12: Empty */
  70         { 0, 0, -1 }, /* P13: Empty */
  71 };