cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / google / rambi / smihandler.c
blob6f652ed1c42b1d50b8a13d970f0f4d71a91e7ea0
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <acpi/acpi.h>
4 #include <console/console.h>
5 #include <cpu/x86/smm.h>
7 #include <ec/google/chromeec/smm.h>
8 #include "ec.h"
10 #include <soc/pm.h>
12 /* The wake gpio is SUS_GPIO[0]. */
13 #define WAKE_GPIO_EN SUS_GPIO_EN0
15 /* The entire 32-bit ALT_GPIO_SMI register is passed as a parameter. Note, that
16 * this includes the enable bits in the lower 16 bits. */
17 void mainboard_smi_gpi(uint32_t alt_gpio_smi)
19 if (alt_gpio_smi & (1 << EC_SMI_GPI))
20 chromeec_smi_process_events();
23 void mainboard_smi_sleep(uint8_t slp_typ)
25 /* Disable USB charging if required */
26 chromeec_set_usb_charge_mode(slp_typ);
28 switch (slp_typ) {
29 case ACPI_S3:
30 /* Enable wake pin in GPE block. */
31 enable_gpe(WAKE_GPIO_EN);
32 break;
35 chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
38 int mainboard_smi_apmc(uint8_t apmc)
40 chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
41 return 0;