src/mainboard/google/skyrim/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <amdblocks/acpi.h>
   4 #include <amdblocks/acpimmio.h>
   5 #include <amdblocks/amd_pci_util.h>
   6 #include <amdblocks/psp.h>
   7 #include <amdblocks/xhci.h>
   8 #include <baseboard/variants.h>
   9 #include <console/console.h>
  10 #include <cpu/x86/smm.h>
  11 #include <device/device.h>
  12 #include <drivers/i2c/tpm/chip.h>
  13 #include <variant/ec.h>
  14
  15 /* The IRQ mapping in fch_irq_map ends up getting written to the indirect address space that is
  16    accessed via I/O ports 0xc00/0xc01. */
  17
  18 /*
  19  * This controls the device -> IRQ routing.
  20  *
  21  * Hardcoded IRQs:
  22  *  0: timer < soc/amd/common/acpi/lpc.asl
  23  *  1: i8042 - Keyboard
  24  *  2: cascade
  25  *  8: rtc0 <- soc/amd/common/acpi/lpc.asl
  26  *  9: acpi <- soc/amd/common/acpi/lpc.asl
  27  */
  28
  29 static const struct fch_irq_routing fch_irq_map[] = {
  30         { PIRQ_A,       12,             PIRQ_NC },
  31         { PIRQ_B,       14,             PIRQ_NC },
  32         { PIRQ_C,       15,             PIRQ_NC },
  33         { PIRQ_D,       12,             PIRQ_NC },
  34         { PIRQ_E,       14,             PIRQ_NC },
  35         { PIRQ_F,       15,             PIRQ_NC },
  36         { PIRQ_G,       12,             PIRQ_NC },
  37         { PIRQ_H,       14,             PIRQ_NC },
  38
  39         { PIRQ_SCI,     ACPI_SCI_IRQ,   ACPI_SCI_IRQ },
  40         { PIRQ_SD,      PIRQ_NC,        PIRQ_NC },
  41         { PIRQ_SDIO,    PIRQ_NC,        PIRQ_NC },
  42         { PIRQ_GPIO,    11,             11 },
  43         { PIRQ_I2C0,    10,             10 },
  44         { PIRQ_I2C1,     7,              7 },
  45         { PIRQ_I2C2,     6,              6 },
  46         { PIRQ_I2C3,     5,              5 },
  47         { PIRQ_UART0,    4,              4 },
  48         { PIRQ_UART1,    3,              3 },
  49
  50         /* The MISC registers are not interrupt numbers */
  51         { PIRQ_MISC,    0xfa,           0x00 },
  52         { PIRQ_MISC0,   0x91,           0x00 },
  53         { PIRQ_HPET_L,  0x00,           0x00 },
  54         { PIRQ_HPET_H,  0x00,           0x00 },
  55 };
  56
  57 const struct fch_irq_routing *mb_get_fch_irq_mapping(size_t *length)
  58 {
  59         *length = ARRAY_SIZE(fch_irq_map);
  60         return fch_irq_map;
  61 }
  62
  63 static void mainboard_configure_gpios(void)
  64 {
  65         size_t base_num_gpios, override_num_gpios;
  66         const struct soc_amd_gpio *base_gpios, *override_gpios;
  67
  68         baseboard_gpio_table(&base_gpios, &base_num_gpios);
  69         variant_override_gpio_table(&override_gpios, &override_num_gpios);
  70
  71         gpio_configure_pads_with_override(base_gpios, base_num_gpios,
  72                                 override_gpios, override_num_gpios);
  73 }
  74
  75 static void configure_psp_tpm_gpio(void)
  76 {
  77         const struct device *ti50_dev = DEV_PTR(ti50);
  78         struct drivers_i2c_tpm_config *cfg = config_of(ti50_dev);
  79
  80         psp_set_tpm_irq_gpio(cfg->irq_gpio.pins[0]);
  81 }
  82
  83 static void mainboard_init(void *chip_info)
  84 {
  85         mainboard_configure_gpios();
  86         mainboard_ec_init();
  87         configure_psp_tpm_gpio();
  88 }
  89
  90 static void mainboard_enable(struct device *dev)
  91 {
  92         /* TODO: b/184678786 - Move into espi_config */
  93         /* Unmask eSPI IRQ 1 (Keyboard) */
  94         pm_write32(PM_ESPI_INTR_CTRL, PM_ESPI_DEV_INTR_MASK & ~(BIT(1)));
  95 }
  96
  97 void smm_mainboard_pci_resource_store_init(struct smm_pci_resource_info *slots, size_t size)
  98 {
  99         soc_xhci_store_resources(slots, size);
 100 }
 101
 102 struct chip_operations mainboard_ops = {
 103         .init = mainboard_init,
 104         .enable_dev = mainboard_enable,
 105 };