cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / intel / saddlebrook / bootblock.c
blob6abc4c596f2234d9d4c8c039ecd4c255cda0a01a
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <bootblock_common.h>
4 #include <soc/gpio.h>
5 #include "gpio.h"
7 #include <superio/nuvoton/common/nuvoton.h>
8 #include <superio/nuvoton/nct6776/nct6776.h>
10 #define SERIAL_DEV PNP_DEV(0x2e, NCT6776_SP1)
12 static void early_config_gpio(void)
14 /* This is a hack for FSP because it does things in MemoryInit()
15 * which it shouldn't do. We have to prepare certain gpios here
16 * because of the brokenness in FSP. */
17 gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
20 void bootblock_mainboard_init(void)
22 early_config_gpio();
25 void bootblock_mainboard_early_init(void)
27 nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);