cpu/x86/smm/pci_resource_store: Store DEV/VEN ID
[coreboot2.git] / src / mainboard / intel / saddlebrook / cmos.layout
blob5a92ae07c97c42a0f551e7ba7b16c332cc892b5c
1 ## SPDX-License-Identifier: GPL-2.0-only
3 # -----------------------------------------------------------------
4 entries
6 #start-bit length  config config-ID     name
8 # -----------------------------------------------------------------
9 0       120     r       0       reserved_memory
11 # -----------------------------------------------------------------
12 # RTC_BOOT_BYTE (coreboot hardcoded)
13 384     1       e       4       boot_option
14 388     4       h       0       reboot_counter
16 # -----------------------------------------------------------------
17 # coreboot config options: console
18 392     3       r       0       unused
19 395     4       e       6       debug_level
21 # coreboot config options: cpu
23 # coreboot config options: southbridge
24 409     2       e       7       power_on_after_fail
26 # coreboot config options: bootloader
28 # coreboot config options: check sums
29 984     16      h       0       check_sum
31 # -----------------------------------------------------------------
33 enumerations
35 #ID     value   text
36 1       0       Disable
37 1       1       Enable
38 2       0       Enable
39 2       1       Disable
40 4       0       Fallback
41 4       1       Normal
42 6       0       Emergency
43 6       1       Alert
44 6       2       Critical
45 6       3       Error
46 6       4       Warning
47 6       5       Notice
48 6       6       Info
49 6       7       Debug
50 6       8       Spew
51 7       0       Disable
52 7       1       Enable
53 7       2       Keep
54 # -----------------------------------------------------------------
55 checksums
57 checksum 392 415 984