| blob | f15e86af2f8af11940ece0c3e5b9097e2466cde0 |
1 /* SPDX-License-Identifier: GPL-2.0-only */
9 }
14 /* The OS can use this MSR to determine "slot" information for the
15 * processor and the proper microcode update to load. */
27 }},
30 PRESENT_DEC, {
32 }},
35 }},
41 }},
44 }},
50 }},
53 }},
59 }},
65 }},
70 }},
75 }},
80 }},
85 }},
90 }},
96 }},
101 }},
106 }},
111 }},
114 }},
116 /* This field indicates the intended scalable bus clock speed */
127 }},
129 }},
136 }},
139 /* Until this bit is set the processor will not respond
140 * to the WBINVD instruction or the assertion
141 * of the FLUSH# input. */
145 }},
151 }},
153 }},
156 }},
158 // Per core msrs
163 }},
167 }},
170 }},
173 }},
175 /* In Intel's manual there is MAXPHYWID,
176 * which determine index of highest bit of
177 * APIC Base itself, so marking it as
178 * 'RESERVED'.
179 */
183 }},
188 }},
191 }},
195 /* if CPUID.01H: ECX[6] = 1 */
200 }},
201 /* if CPUID.01H: ECX[6] = 1 */
204 }},
210 }},
211 /* if CPUID.01H: ECX[5 or 6] = 1 */
213 /* This bit enables VMX for system executive
214 * that do not require SMX.
215 */
219 }},
221 /* This bit enables a system executive to use
222 * VMX in conjunction with SMX to support Intel
223 * Trusted Execution Technology.
224 */
228 }},
229 /* if CPUID.01H: ECX[5 or 6] = 1 */
231 /* Once the Lock bit is set, the contents
232 * of this register cannot be modified.
233 * Therefore the lock bit must be set after
234 * configuring support for Intel Virtualization
235 * Technology and prior transferring control
236 * to an Option ROM or bootloader. Hence, once
237 * the lock bit is set, the entire IA32_FEATURE_CONTROL_MSR
238 * contents are preserved across RESET when
239 * PWRGOOD it not deasserted.
240 */
244 }},
246 }},
249 }},
252 }},
255 }},
258 }},
261 }},
264 }},
267 }},
270 }},
274 }},
278 }},
281 }},
284 }},
287 }},
290 }},
293 }},
296 }},
301 }},
304 }},
307 }},
310 }},
313 }},
316 }},
320 /* When set, bit indicates that a machine check has been
321 * generated. If a second machine check is detected while
322 * this bit is still set, the processor enters a shutdown state.
323 * Software should write this bit to 0 after processing
324 * a machine check exception.
325 */
329 }},
331 /* When set, bit indicates that the instruction addressed
332 * by the instruction pointer pushed on the stack (when
333 * the machine check was generated) is directly associated
334 * with the error
335 */
339 }},
341 /* When set, bit indicates that the instruction addressed
342 * by the instruction pointer pushed on the stack (when
343 * the machine check was generated) can be used to restart
344 * the program. If cleared, the program cannot be reliably restarted
345 */
349 }},
351 }},
352 /* if CPUID.0AH: EAX[15:8] > 0 */
357 /* When CMASK is not zero, the corresponding performance
358 * counter 0 increments each cycle if the event count
359 * is greater than or equal to the CMASK.
360 */
362 }},
367 }},
372 }},
375 }},
380 }},
385 }},
390 }},
395 }},
400 }},
402 /* Qualifies the microarchitectural condition
403 * to detect on the selected event logic. */
405 }},
407 /* Selects a performance event logic unit. */
409 }},
411 }},
412 /* if CPUID.0AH: EAX[15:8] > 0 */
417 /* When CMASK is not zero, the corresponding performance
418 * counter 1 increments each cycle if the event count
419 * is greater than or equal to the CMASK.
420 */
422 }},
427 }},
432 }},
435 }},
440 }},
445 }},
450 }},
455 }},
460 }},
462 /* Qualifies the microarchitectural condition
463 * to detect on the selected event logic. */
465 }},
467 /* Selects a performance event logic unit. */
469 }},
471 }},
474 }},
477 }},
485 }},
488 }},
491 }},
495 }},
499 }},
502 }},
510 }},
511 /* Note: [38] bit using for whole package,
512 * while some other bits can be Core or Thread
513 * specific.
514 */
516 /* When set to a 0 on processors that support IDA,
517 * CPUID.06H: EAX[1] reports the processor's
518 * support of turbo mode is enabled.
519 */
521 /* When set 1 on processors that support Intel Turbo Boost
522 * technology, the turbo mode feature is disabled and
523 * the IDA_Enable feature flag will be clear (CPUID.06H: EAX[1]=0).
524 */
527 /* Note: the power-on default value is used by BIOS to detect
528 * hardware support of turbo mode. If power-on default value is 1,
529 * turbo mode is available in the processor. If power-on default
530 * value is 0, turbo mode not available.
531 */
532 }},
537 }},
541 }},
545 }},
548 }},
551 PRESENT_BIN, {
557 }},
559 PRESENT_BIN, {
565 }},
568 }},
571 }},
572 /* Note: [16] bit using for whole package,
573 * while some other bits can be Core or Thread
574 * specific.
575 */
577 PRESENT_BIN, {
579 }},
583 }},
585 PRESENT_BIN, {
587 }},
590 }},
596 }},
601 }},
605 }},
610 }},
614 }},
616 }},
619 }},
622 }},
625 }},
628 }},
631 }},
634 }},
637 }},
640 }},
643 }},
646 }},
649 }},
652 }},
655 }},
658 }},
661 }},
664 }},
667 }},
670 }},
673 }},
676 }},
679 }},
682 }},
685 }},
688 }},
691 }},
694 }},
697 }},
700 }},
703 }},
706 }},
709 }},
714 }},
718 }},
722 }},
726 }},
730 }},
734 }},
738 }},
742 }},
744 }},
750 }},
753 }},
757 }},
759 }},
760 /* if CPUID.0AH: EDX[4:0] > 0 */
763 /* Also known as MSR_PERF_FIXED_CTR0 */
765 }},
766 /* if CPUID.0AH: EDX[4:0] > 1 */
769 /* Also known as MSR_PERF_FIXED_CTR1 */
771 }},
772 /* if CPUID.0AH: EDX[4:0] > 2 */
775 /* Also known as MSR_PERF_FIXED_CTR2 */
777 }},
779 /* Additional info available at Section 17.4.1 of
780 * Intel 64 and IA-32 Architectures Software Developer's
781 * Manual, Volume 3.
782 */
786 }},
789 }},
792 }},
794 }},
795 /* if CPUID.0AH: EAX[7:0] > 1*/
798 /* Also known as MSR_PERF_FIXED_CTR_CTRL.
799 * Counter increments while the results of ANDing respective enable bit
800 * in IA32_PERF_GLOBAL_CTRL with the corresponding OS or USR bits
801 * in this MSR is true. */
807 }},
808 /* if CPUID.0AH EAX[7:0] > 2 */
811 "conditions occurring in the logical processor "
814 "occurring across all logical processors sharing "
817 }},
822 }},
827 }},
832 }},
833 /* if CPUID.0AH: EAX[7:0] > 2 */
836 "conditions occurring in the logical processor "
839 "occurring across all logical processors sharing "
842 }},
847 }},
852 }},
857 }},
858 /* if CPUID.0AH: EAX[7:0] > 2 */
861 "conditions occurring in the logical processor "
864 "occurring across all logical processors sharing "
867 }},
872 }},
877 }},
879 }},
880 /* if CPUID.0AH: EAX[7:0] > 0 */
883 /* Also known as MSR_PERF_GLOBAL_STATUS */
884 /* if CPUID.0AH: EAX[7:0] > 0 */
888 }},
889 /* if CPUID.0AH: EAX[7:0] > 0 */
893 }},
894 /* if CPUID.0AH: EAX[7:0] > 2 */
898 }},
900 /* if CPUID.0AH: EAX[7:0] > 1 */
904 }},
905 /* if CPUID.0AH: EAX[7:0] > 1 */
909 }},
910 /* if CPUID.0AH: EAX[7:0] > 1 */
914 }},
916 /* presented only in 06_2EH Nehalem model */
919 }},
920 /* presented only in 06_2EH Nehalem model */
923 }},
924 /* if CPUID.0AH: EAX[7:0] > 0 */
927 }},
928 /* if CPUID.0AH: EAX[7:0] > 0 */
931 }},
933 }},
934 /* if CPUID.0AH: EAX[7:0] > 0 */
937 /* Counter increments while the result of ANDing respective
938 * enable bit in this MSR with corresponding OS or USR bits
939 * in general-purpose or fixed counter control MSR is true.
940 */
942 /* if CPUID.0AH: EAX[7:0] > 1 */
945 }},
946 /* if CPUID.0AH: EAX[7:0] > 1 */
949 }},
950 /* if CPUID.0AH: EAX[7:0] > 1 */
953 }},
955 /* if CPUID.0AH: EAX[7:0] > 0 */
958 }},
959 /* if CPUID.0AH: EAX[7:0] > 0 */
962 }},
964 }},
965 /* if CPUID.0AH: EAX[7:0] > 0 */
968 /* if CPUID.0AH: EAX[7:0] > 0 */
971 }},
972 /* if CPUID.0AH: EAX[7:0] > 0 */
975 }},
976 /* Presented only in 06_2EH Nehalem model */
979 }},
981 /* if CPUID.0AH: EAX[7:0] > 1 */
984 }},
985 /* if CPUID.0AH: EAX[7:0] > 1 */
988 }},
989 /* if CPUID.0AH: EAX[7:0] > 1 */
992 }},
994 /* if CPUID.0AH: EAX[7:0] > 0 */
997 }},
998 /* if CPUID.0AH: EAX[7:0] > 0 */
1001 }},
1003 }},
1004 /* See Section 18.6.1.1 of Intel 64 and IA-32 Architectures
1005 * Software Developer's Manual, Volume 3,
1006 * "Precise Event Based Sampling (PEBS)".
1007 */
1014 }},
1019 }},
1024 }},
1029 }},
1035 }},
1040 }},
1045 }},
1050 }},
1052 }},
1055 }},
1058 }},
1061 }},
1064 }},
1067 }},
1070 }},
1073 }},
1076 }},
1079 }},
1082 }},
1085 }},
1088 }},
1091 }},
1094 }},
1097 }},
1100 }},
1103 }},
1106 }},
1109 }},
1112 }},
1115 }},
1118 }},
1121 }},
1124 }},
1127 }},
1130 }},
1133 /* Additional info available at
1134 * Appendix A.1, "Basic VMX Information" */
1138 }},
1142 }},
1145 }},
1149 }},
1152 }},
1154 }},
1156 "Capability Reporting Register of "
1158 /* Additional info available at Appendix A.3,
1159 * "VM-Execution Controls" */
1161 }},
1163 "Capability Reporting Register of "
1165 /* Additional info available at Appendix A.3,
1166 * "VM-Execution Controls" */
1168 }},
1171 /* Additional info available at Appendix A.4,
1172 * "VM-Exit Controls" */
1174 }},
1177 /* Additional info available at Appendix A.5,
1178 * "VM-Entry Controls" */
1180 }},
1183 /* Additional info available at Appendix A.6,
1184 * "Miscellaneous Data" */
1186 }},
1189 /* Additional info available at Appendix A.7,
1190 * "VMX-Fixed Bits in CR0" */
1192 }},
1195 /* Additional info available at Appendix A.7,
1196 * "VMX-Fixed Bits in CR0" */
1198 }},
1201 /* Additional info available at Appendix A.8,
1202 * "VMX-Fixed Bits in CR4" */
1204 }},
1207 /* Additional info available at Appendix A.8,
1208 * "VMX-Fixed Bits in CR4" */
1210 }},
1213 /* Additional info available at Appendix A.9,
1214 * "VMCS Enumeration" */
1216 }},
1218 "Capability Reporting Register of Secondary "
1220 /* Additional info available at Appendix A.3,
1221 * "VM-Execution Controls" */
1223 }},
1225 /* Additional info available at Section 18.10.4 of Intel 64
1226 * and IA-32 Architectures Software Developer's Manual,
1227 * "Debug Store (DS) Mechanism".
1228 */
1233 }},
1235 }},
1238 }},
1241 }},
1244 }},
1247 }},
1250 }},
1253 }},
1256 }},
1259 }},
1262 }},
1265 }},
1268 }},
1271 }},
1274 }},
1277 }},
1280 }},
1283 }},
1285 };