util/bincfg/ifd-x200.set

   1 # SPDX-License-Identifier: GPL-3.0-or-later
   2 #
   3 # X200 Liberated Flash Descriptor
   4 # Layout:
   5 #       0x0000 - 0x1000  : IFD
   6 #       0x1000 - 0x3000  : GbE x2
   7 #       0x3000 - ROMSIZE : BIOS
   8 {
   9         "fd_signature" = 0xff0a55a,
  10
  11         "flmap0_fcba" = 0x1,
  12         "flmap0_nc" = 0x0,
  13         "flmap0_reserved0" = 0x0,
  14         "flmap0_frba" = 0x4,
  15         "flmap0_nr" = 0x3,
  16         "flmap0_reserved1" = 0x0,
  17         "flmap1_fmba" = 0x6,
  18         "flmap1_nm" = 0x2,
  19         "flmap1_reserved" = 0x0,
  20         "flmap1_fisba" = 0x10,
  21         "flmap1_isl" = 0x2,
  22         "flmap2_fmsba" = 0x20,
  23         "flmap2_msl" = 0x1,
  24         "flmap2_reserved" = 0x0,
  25
  26         "flcomp_density1" = 0x4,
  27         "flcomp_density2" = 0x2,
  28         "flcomp_reserved0" = 0x0,
  29         "flcomp_reserved1" = 0x0,
  30         "flcomp_reserved2" = 0x0,
  31         "flcomp_readclockfreq" = 0x0,
  32         "flcomp_fastreadsupp" = 0x1,
  33         "flcomp_fastreadfreq" = 0x1,
  34         "flcomp_w_eraseclkfreq" = 0x0,
  35         "flcomp_r_statclkfreq" = 0x0,
  36         "flcomp_reserved3" = 0x0,
  37         "flill" = 0x0,
  38         "flbp" = 0x0,
  39         "comp_padding"[0x24] = 0xff,
  40
  41         "flreg0_base" = 0x0,
  42         "flreg0_reserved0" = 0x0,
  43         "flreg0_limit" = 0x0,
  44         "flreg0_reserved1" = 0x0,
  45         "flreg1_base" = 0x3,
  46         "flreg1_reserved0" = 0x0,
  47         "flreg1_limit" = 0x7ff,
  48         "flreg1_reserved1" = 0x0,
  49         "flreg2_base" = 0x1fff,
  50         "flreg2_reserved0" = 0x0,
  51         "flreg2_limit" = 0x0,
  52         "flreg2_reserved1" = 0x0,
  53         "flreg3_base" = 0x1,
  54         "flreg3_reserved0" = 0x0,
  55         "flreg3_limit" = 0x2,
  56         "flreg3_reserved1" = 0x0,
  57         "flreg4_base" = 0x1fff,
  58         "flreg4_reserved0" = 0x0,
  59         "flreg4_limit" = 0x0,
  60         "flreg4_reserved1" = 0x0,
  61         "flreg_padding"[12] = 0xff,
  62
  63         "flmstr1_requesterid" = 0x0,
  64         "flmstr1_r_fd" = 0x1,
  65         "flmstr1_r_bios" = 0x1,
  66         "flmstr1_r_me" = 0x1,
  67         "flmstr1_r_gbe" = 0x1,
  68         "flmstr1_r_pd" = 0x1,
  69         "flmstr1_r_reserved" = 0x0,
  70         "flmstr1_w_fd" = 0x1,
  71         "flmstr1_w_bios" = 0x1,
  72         "flmstr1_w_me" = 0x1,
  73         "flmstr1_w_gbe" = 0x1,
  74         "flmstr1_w_pd" = 0x1,
  75         "flmstr1_w_reserved" = 0x0,
  76         "flmstr2_requesterid" = 0x0,
  77         "flmstr2_r_fd" = 0x0,
  78         "flmstr2_r_bios" = 0x0,
  79         "flmstr2_r_me" = 0x0,
  80         "flmstr2_r_gbe" = 0x0,
  81         "flmstr2_r_pd" = 0x0,
  82         "flmstr2_r_reserved" = 0x0,
  83         "flmstr2_w_fd" = 0x0,
  84         "flmstr2_w_bios" = 0x0,
  85         "flmstr2_w_me" = 0x0,
  86         "flmstr2_w_gbe" = 0x0,
  87         "flmstr2_w_pd" = 0x0,
  88         "flmstr2_w_reserved" = 0x0,
  89         "flmstr3_requesterid" = 0x218,
  90         "flmstr3_r_fd" = 0x0,
  91         "flmstr3_r_bios" = 0x0,
  92         "flmstr3_r_me" = 0x0,
  93         "flmstr3_r_gbe" = 0x1,
  94         "flmstr3_r_pd" = 0x0,
  95         "flmstr3_r_reserved" = 0x0,
  96         "flmstr3_w_fd" = 0x0,
  97         "flmstr3_w_bios" = 0x0,
  98         "flmstr3_w_me" = 0x0,
  99         "flmstr3_w_gbe" = 0x1,
 100         "flmstr3_w_pd" = 0x0,
 101         "flmstr3_w_reserved" = 0x0,
 102         "flmstr_padding"[0x94] = 0xff,
 103
 104         "ich0_medisable" = 0x1,
 105         "ich0_reserved0" = 0x4,
 106         "ich0_tcomode" = 0x1,
 107         "ich0_mesmbusaddr" = 0x64,
 108         "ich0_bmcmode" = 0x0,
 109         "ich0_trippointsel" = 0x0,
 110         "ich0_reserved1" = 0x0,
 111         "ich0_integratedgbe" = 0x1,
 112         "ich0_lanphy" = 0x1,
 113         "ich0_reserved2" = 0x0,
 114         "ich0_dmireqiddisable" = 0x0,
 115         "ich0_me2smbusaddr" = 0x0,
 116         "ich1_dynclk_nmlink" = 0x1,
 117         "ich1_dynclk_smlink" = 0x1,
 118         "ich1_dynclk_mesmbus" = 0x1,
 119         "ich1_dynclk_sst" = 0x1,
 120         "ich1_reserved0" = 0x0,
 121         "ich1_nmlink_npostreqs" = 0x1,
 122         "ich1_reserved1" = 0x0,
 123         "ich1_reserved2" = 0x0,
 124         "ichstrap_padding"[0xf8] = 0xff,
 125         "mch0_medisable" = 0x1,
 126         "mch0_mebootfromflash" = 0x0,
 127         "mch0_tpmdisable" = 0x1,
 128         "mch0_reserved0" = 0x7,
 129         "mch0_spifingerprinton" = 0x1,
 130         "mch0_mealtdisable" = 0x0,
 131         "mch0_reserved1" = 0xff,
 132         "mch0_reserved2" = 0xffff,
 133         "mchstrap_padding"[0xcdc] = 0xff,
 134
 135         "mevscc_jid0" = 0x1720c2,
 136         "mevscc_vscc0" = 0x20052005,
 137         "mevscc_jid1" = 0x1730ef,
 138         "mevscc_vscc1" = 0x20052005,
 139         "mevscc_jid2" = 0x481f,
 140         "mevscc_vscc2" = 0x20152015,
 141         "mevscc_padding"[4] = 0xff,
 142         "mevscc_tablebase" = 0xee,
 143         "mevscc_tablelength" = 0x6,
 144         "mevscc_reserved" = 0x0,
 145
 146         "oem_magic0" = 0x4c,
 147         "oem_magic1" = 0x49,
 148         "oem_magic2" = 0x42,
 149         "oem_magic3" = 0x45,
 150         "oem_magic4" = 0x52,
 151         "oem_magic5" = 0x41,
 152         "oem_magic6" = 0x54,
 153         "oem_magic7" = 0x45,
 154         "oem_padding"[0xf8] = 0xff
 155 }