src/include/reg_script.h

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #ifndef REG_SCRIPT_H
   4 #define REG_SCRIPT_H
   5
   6 #include <stdint.h>
   7 #include <device/device.h>
   8 #include <device/pci_type.h>
   9
  10 /*
  11  * The reg script library is a way to provide data-driven I/O accesses for
  12  * initializing devices. It currently supports PCI, legacy I/O,
  13  * memory-mapped I/O, and IOSF accesses.
  14  *
  15  * In order to simplify things for the developer the following features
  16  * are employed:
  17  * - Chaining of tables that allow runtime tables to chain to compile-time
  18  *   tables.
  19  *
  20  * Note that when using REG_SCRIPT_COMMAND_NEXT there is an implicit push
  21  * and pop of the context. A chained reg_script inherits the previous
  22  * context (such as current device), but it does not impact the previous
  23  * context in any way.
  24  */
  25
  26 enum {
  27         REG_SCRIPT_COMMAND_READ,
  28         REG_SCRIPT_COMMAND_WRITE,
  29         REG_SCRIPT_COMMAND_RMW,
  30         REG_SCRIPT_COMMAND_RXW,
  31         REG_SCRIPT_COMMAND_POLL,
  32         REG_SCRIPT_COMMAND_SET_DEV,
  33         REG_SCRIPT_COMMAND_NEXT,
  34         REG_SCRIPT_COMMAND_DISPLAY,
  35
  36         /* Insert new types above this comment */
  37
  38         REG_SCRIPT_COMMAND_END,
  39 };
  40
  41 enum {
  42         REG_SCRIPT_TYPE_PCI,
  43         REG_SCRIPT_TYPE_IO,
  44         REG_SCRIPT_TYPE_MMIO,
  45         REG_SCRIPT_TYPE_RES,
  46         REG_SCRIPT_TYPE_IOSF,
  47         REG_SCRIPT_TYPE_MSR,
  48
  49         /* Insert other platform independent values above this comment */
  50
  51         REG_SCRIPT_TYPE_PLATFORM_BASE = 0x10000,
  52         REG_SCRIPT_TYPE_SOC_BASE = REG_SCRIPT_TYPE_PLATFORM_BASE,
  53         REG_SCRIPT_TYPE_MAINBOARD_BASE = 0x20000
  54 };
  55
  56 enum {
  57         REG_SCRIPT_SIZE_8,
  58         REG_SCRIPT_SIZE_16,
  59         REG_SCRIPT_SIZE_32,
  60         REG_SCRIPT_SIZE_64,
  61 };
  62
  63 struct reg_script {
  64         uint32_t command;
  65         uint32_t type;
  66         uint32_t size;
  67         uint32_t reg;
  68         uint64_t mask;
  69         uint64_t value;
  70         uint32_t timeout;
  71         union {
  72                 uint32_t id;
  73                 const struct reg_script *next;
  74 #ifdef __SIMPLE_DEVICE__
  75                 pci_devfn_t dev;
  76 #else
  77                 struct device *dev;
  78 #endif
  79                 unsigned int res_index;
  80         };
  81 };
  82
  83 struct reg_script_context {
  84 #ifdef __SIMPLE_DEVICE__
  85         pci_devfn_t dev;
  86 #else
  87         struct device *dev;
  88 #endif
  89         struct resource *res;
  90         const struct reg_script *step;
  91         uint8_t display_state;    /* Only modified by reg_script_run_step */
  92         uint8_t display_features; /* Step routine modifies to control display */
  93         const char *display_prefix; /* Prefix tag to display */
  94 };
  95
  96 struct reg_script_bus_entry {
  97         uint32_t type;
  98         uint64_t (*reg_script_read)(struct reg_script_context *ctx);
  99         void (*reg_script_write)(struct reg_script_context *ctx);
 100 };
 101
 102 #define REG_SCRIPT_TABLE_ATTRIBUTE __attribute__((used, section(".rsbe_init")))
 103
 104 #define REG_SCRIPT_BUS_ENTRY(bus_entry_)                                \
 105         const struct reg_script_bus_entry *rsbe_ ## bus_entry_  \
 106                 REG_SCRIPT_TABLE_ATTRIBUTE = &bus_entry_
 107
 108 /* Internal helper Macros. */
 109
 110 #define _REG_SCRIPT_ENCODE_RAW(cmd_, type_, size_, reg_, \
 111                           mask_, value_, timeout_, id_)  \
 112         { .command = cmd_,     \
 113           .type = type_,       \
 114           .size = size_,       \
 115           .reg = reg_,         \
 116           .mask = mask_,       \
 117           .value = value_,     \
 118           .timeout = timeout_, \
 119           .id = id_,           \
 120         }
 121
 122 #define _REG_SCRIPT_ENCODE_RES(cmd_, type_, res_index_, size_, reg_, \
 123                                mask_, value_, timeout_)  \
 124         { .command = cmd_,         \
 125           .type = type_,           \
 126           .size = size_,           \
 127           .reg = reg_,             \
 128           .mask = mask_,           \
 129           .value = value_,         \
 130           .timeout = timeout_,     \
 131           .res_index = res_index_, \
 132         }
 133
 134 /* Display control */
 135 #define REG_SCRIPT_DISPLAY_ALL          0xff
 136 #define REG_SCRIPT_DISPLAY_REGISTER     0x02
 137 #define REG_SCRIPT_DISPLAY_VALUE        0x01
 138 #define REG_SCRIPT_DISPLAY_NOTHING      0
 139
 140 #define REG_SCRIPT_DISPLAY_OFF                   \
 141         { .command = REG_SCRIPT_COMMAND_DISPLAY, \
 142           .value = REG_SCRIPT_DISPLAY_NOTHING,   \
 143         }
 144 #define REG_SCRIPT_DISPLAY_ON                    \
 145         { .command = REG_SCRIPT_COMMAND_DISPLAY, \
 146           .value = REG_SCRIPT_DISPLAY_ALL,       \
 147         }
 148
 149 /*
 150  * PCI
 151  */
 152
 153 #define REG_SCRIPT_PCI(cmd_, bits_, reg_, mask_, value_, timeout_) \
 154         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,          \
 155                                REG_SCRIPT_TYPE_PCI,                \
 156                                REG_SCRIPT_SIZE_##bits_,            \
 157                                reg_, mask_, value_, timeout_, 0)
 158 #define REG_PCI_READ8(reg_) \
 159         REG_SCRIPT_PCI(READ, 8, reg_, 0, 0, 0)
 160 #define REG_PCI_READ16(reg_) \
 161         REG_SCRIPT_PCI(READ, 16, reg_, 0, 0, 0)
 162 #define REG_PCI_READ32(reg_) \
 163         REG_SCRIPT_PCI(READ, 32, reg_, 0, 0, 0)
 164 #define REG_PCI_WRITE8(reg_, value_) \
 165         REG_SCRIPT_PCI(WRITE, 8, reg_, 0, value_, 0)
 166 #define REG_PCI_WRITE16(reg_, value_) \
 167         REG_SCRIPT_PCI(WRITE, 16, reg_, 0, value_, 0)
 168 #define REG_PCI_WRITE32(reg_, value_) \
 169         REG_SCRIPT_PCI(WRITE, 32, reg_, 0, value_, 0)
 170 #define REG_PCI_RMW8(reg_, mask_, value_) \
 171         REG_SCRIPT_PCI(RMW, 8, reg_, mask_, value_, 0)
 172 #define REG_PCI_RMW16(reg_, mask_, value_) \
 173         REG_SCRIPT_PCI(RMW, 16, reg_, mask_, value_, 0)
 174 #define REG_PCI_RMW32(reg_, mask_, value_) \
 175         REG_SCRIPT_PCI(RMW, 32, reg_, mask_, value_, 0)
 176 #define REG_PCI_RXW8(reg_, mask_, value_) \
 177         REG_SCRIPT_PCI(RXW, 8, reg_, mask_, value_, 0)
 178 #define REG_PCI_RXW16(reg_, mask_, value_) \
 179         REG_SCRIPT_PCI(RXW, 16, reg_, mask_, value_, 0)
 180 #define REG_PCI_RXW32(reg_, mask_, value_) \
 181         REG_SCRIPT_PCI(RXW, 32, reg_, mask_, value_, 0)
 182 #define REG_PCI_OR8(reg_, value_) \
 183         REG_SCRIPT_PCI(RMW, 8, reg_, 0xff, value_, 0)
 184 #define REG_PCI_OR16(reg_, value_) \
 185         REG_SCRIPT_PCI(RMW, 16, reg_, 0xffff, value_, 0)
 186 #define REG_PCI_OR32(reg_, value_) \
 187         REG_SCRIPT_PCI(RMW, 32, reg_, 0xffffffff, value_, 0)
 188 #define REG_PCI_POLL8(reg_, mask_, value_, timeout_) \
 189         REG_SCRIPT_PCI(POLL, 8, reg_, mask_, value_, timeout_)
 190 #define REG_PCI_POLL16(reg_, mask_, value_, timeout_) \
 191         REG_SCRIPT_PCI(POLL, 16, reg_, mask_, value_, timeout_)
 192 #define REG_PCI_POLL32(reg_, mask_, value_, timeout_) \
 193         REG_SCRIPT_PCI(POLL, 32, reg_, mask_, value_, timeout_)
 194 #define REG_PCI_XOR8(reg_, value_) \
 195         REG_SCRIPT_PCI(RXW, 8, reg_, 0xff, value_, 0)
 196 #define REG_PCI_XOR16(reg_, value_) \
 197         REG_SCRIPT_PCI(RXW, 16, reg_, 0xffff, value_, 0)
 198 #define REG_PCI_XOR32(reg_, value_) \
 199         REG_SCRIPT_PCI(RXW, 32, reg_, 0xffffffff, value_, 0)
 200
 201 /*
 202  * Legacy IO
 203  */
 204
 205 #define REG_SCRIPT_IO(cmd_, bits_, reg_, mask_, value_, timeout_) \
 206         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,         \
 207                                REG_SCRIPT_TYPE_IO,                \
 208                                REG_SCRIPT_SIZE_##bits_,           \
 209                                reg_, mask_, value_, timeout_, 0)
 210 #define REG_IO_READ8(reg_) \
 211         REG_SCRIPT_IO(READ, 8, reg_, 0, 0, 0)
 212 #define REG_IO_READ16(reg_) \
 213         REG_SCRIPT_IO(READ, 16, reg_, 0, 0, 0)
 214 #define REG_IO_READ32(reg_) \
 215         REG_SCRIPT_IO(READ, 32, reg_, 0, 0, 0)
 216 #define REG_IO_WRITE8(reg_, value_) \
 217         REG_SCRIPT_IO(WRITE, 8, reg_, 0, value_, 0)
 218 #define REG_IO_WRITE16(reg_, value_) \
 219         REG_SCRIPT_IO(WRITE, 16, reg_, 0, value_, 0)
 220 #define REG_IO_WRITE32(reg_, value_) \
 221         REG_SCRIPT_IO(WRITE, 32, reg_, 0, value_, 0)
 222 #define REG_IO_RMW8(reg_, mask_, value_) \
 223         REG_SCRIPT_IO(RMW, 8, reg_, mask_, value_, 0)
 224 #define REG_IO_RMW16(reg_, mask_, value_) \
 225         REG_SCRIPT_IO(RMW, 16, reg_, mask_, value_, 0)
 226 #define REG_IO_RMW32(reg_, mask_, value_) \
 227         REG_SCRIPT_IO(RMW, 32, reg_, mask_, value_, 0)
 228 #define REG_IO_RXW8(reg_, mask_, value_) \
 229         REG_SCRIPT_IO(RXW, 8, reg_, mask_, value_, 0)
 230 #define REG_IO_RXW16(reg_, mask_, value_) \
 231         REG_SCRIPT_IO(RXW, 16, reg_, mask_, value_, 0)
 232 #define REG_IO_RXW32(reg_, mask_, value_) \
 233         REG_SCRIPT_IO(RXW, 32, reg_, mask_, value_, 0)
 234 #define REG_IO_OR8(reg_, value_) \
 235         REG_IO_RMW8(reg_, 0xff, value_)
 236 #define REG_IO_OR16(reg_, value_) \
 237         REG_IO_RMW16(reg_, 0xffff, value_)
 238 #define REG_IO_OR32(reg_, value_) \
 239         REG_IO_RMW32(reg_, 0xffffffff, value_)
 240 #define REG_IO_POLL8(reg_, mask_, value_, timeout_) \
 241         REG_SCRIPT_IO(POLL, 8, reg_, mask_, value_, timeout_)
 242 #define REG_IO_POLL16(reg_, mask_, value_, timeout_) \
 243         REG_SCRIPT_IO(POLL, 16, reg_, mask_, value_, timeout_)
 244 #define REG_IO_POLL32(reg_, mask_, value_, timeout_) \
 245         REG_SCRIPT_IO(POLL, 32, reg_, mask_, value_, timeout_)
 246 #define REG_IO_XOR8(reg_, value_) \
 247         REG_IO_RXW8(reg_, 0xff, value_)
 248 #define REG_IO_XOR16(reg_, value_) \
 249         REG_IO_RXW16(reg_, 0xffff, value_)
 250 #define REG_IO_XOR32(reg_, value_) \
 251         REG_IO_RXW32(reg_, 0xffffffff, value_)
 252
 253 /*
 254  * Memory Mapped IO
 255  */
 256
 257 #define REG_SCRIPT_MMIO(cmd_, bits_, reg_, mask_, value_, timeout_) \
 258         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,           \
 259                                REG_SCRIPT_TYPE_MMIO,                \
 260                                REG_SCRIPT_SIZE_##bits_,             \
 261                                reg_, mask_, value_, timeout_, 0)
 262 #define REG_MMIO_READ8(reg_) \
 263         REG_SCRIPT_MMIO(READ, 8, reg_, 0, 0, 0)
 264 #define REG_MMIO_READ16(reg_) \
 265         REG_SCRIPT_MMIO(READ, 16, reg_, 0, 0, 0)
 266 #define REG_MMIO_READ32(reg_) \
 267         REG_SCRIPT_MMIO(READ, 32, reg_, 0, 0, 0)
 268 #define REG_MMIO_WRITE8(reg_, value_) \
 269         REG_SCRIPT_MMIO(WRITE, 8, reg_, 0, value_, 0)
 270 #define REG_MMIO_WRITE16(reg_, value_) \
 271         REG_SCRIPT_MMIO(WRITE, 16, reg_, 0, value_, 0)
 272 #define REG_MMIO_WRITE32(reg_, value_) \
 273         REG_SCRIPT_MMIO(WRITE, 32, reg_, 0, value_, 0)
 274 #define REG_MMIO_RMW8(reg_, mask_, value_) \
 275         REG_SCRIPT_MMIO(RMW, 8, reg_, mask_, value_, 0)
 276 #define REG_MMIO_RMW16(reg_, mask_, value_) \
 277         REG_SCRIPT_MMIO(RMW, 16, reg_, mask_, value_, 0)
 278 #define REG_MMIO_RMW32(reg_, mask_, value_) \
 279         REG_SCRIPT_MMIO(RMW, 32, reg_, mask_, value_, 0)
 280 #define REG_MMIO_RXW8(reg_, mask_, value_) \
 281         REG_SCRIPT_MMIO(RXW, 8, reg_, mask_, value_, 0)
 282 #define REG_MMIO_RXW16(reg_, mask_, value_) \
 283         REG_SCRIPT_MMIO(RXW, 16, reg_, mask_, value_, 0)
 284 #define REG_MMIO_RXW32(reg_, mask_, value_) \
 285         REG_SCRIPT_MMIO(RXW, 32, reg_, mask_, value_, 0)
 286 #define REG_MMIO_OR8(reg_, value_) \
 287         REG_MMIO_RMW8(reg_, 0xff, value_)
 288 #define REG_MMIO_OR16(reg_, value_) \
 289         REG_MMIO_RMW16(reg_, 0xffff, value_)
 290 #define REG_MMIO_OR32(reg_, value_) \
 291         REG_MMIO_RMW32(reg_, 0xffffffff, value_)
 292 #define REG_MMIO_POLL8(reg_, mask_, value_, timeout_) \
 293         REG_SCRIPT_MMIO(POLL, 8, reg_, mask_, value_, timeout_)
 294 #define REG_MMIO_POLL16(reg_, mask_, value_, timeout_) \
 295         REG_SCRIPT_MMIO(POLL, 16, reg_, mask_, value_, timeout_)
 296 #define REG_MMIO_POLL32(reg_, mask_, value_, timeout_) \
 297         REG_SCRIPT_MMIO(POLL, 32, reg_, mask_, value_, timeout_)
 298 #define REG_MMIO_XOR8(reg_, value_) \
 299         REG_MMIO_RXW8(reg_, 0xff, value_)
 300 #define REG_MMIO_XOR16(reg_, value_) \
 301         REG_MMIO_RXW16(reg_, 0xffff, value_)
 302 #define REG_MMIO_XOR32(reg_, value_) \
 303         REG_MMIO_RXW32(reg_, 0xffffffff, value_)
 304
 305 /*
 306  * Access through a device's resource such as a Base Address Register (BAR)
 307  */
 308
 309 #define REG_SCRIPT_RES(cmd_, bits_, bar_, reg_, mask_, value_, timeout_) \
 310         _REG_SCRIPT_ENCODE_RES(REG_SCRIPT_COMMAND_##cmd_,                \
 311                                REG_SCRIPT_TYPE_RES, bar_,                \
 312                                REG_SCRIPT_SIZE_##bits_,                  \
 313                                reg_, mask_, value_, timeout_)
 314 #define REG_RES_READ8(bar_, reg_) \
 315         REG_SCRIPT_RES(READ, 8, bar_, reg_, 0, 0, 0)
 316 #define REG_RES_READ16(bar_, reg_) \
 317         REG_SCRIPT_RES(READ, 16, bar_, reg_, 0, 0, 0)
 318 #define REG_RES_READ32(bar_, reg_) \
 319         REG_SCRIPT_RES(READ, 32, bar_, reg_, 0, 0, 0)
 320 #define REG_RES_WRITE8(bar_, reg_, value_) \
 321         REG_SCRIPT_RES(WRITE, 8, bar_, reg_, 0, value_, 0)
 322 #define REG_RES_WRITE16(bar_, reg_, value_) \
 323         REG_SCRIPT_RES(WRITE, 16, bar_, reg_, 0, value_, 0)
 324 #define REG_RES_WRITE32(bar_, reg_, value_) \
 325         REG_SCRIPT_RES(WRITE, 32, bar_, reg_, 0, value_, 0)
 326 #define REG_RES_RMW8(bar_, reg_, mask_, value_) \
 327         REG_SCRIPT_RES(RMW, 8, bar_, reg_, mask_, value_, 0)
 328 #define REG_RES_RMW16(bar_, reg_, mask_, value_) \
 329         REG_SCRIPT_RES(RMW, 16, bar_, reg_, mask_, value_, 0)
 330 #define REG_RES_RMW32(bar_, reg_, mask_, value_) \
 331         REG_SCRIPT_RES(RMW, 32, bar_, reg_, mask_, value_, 0)
 332 #define REG_RES_RXW8(bar_, reg_, mask_, value_) \
 333         REG_SCRIPT_RES(RXW, 8, bar_, reg_, mask_, value_, 0)
 334 #define REG_RES_RXW16(bar_, reg_, mask_, value_) \
 335         REG_SCRIPT_RES(RXW, 16, bar_, reg_, mask_, value_, 0)
 336 #define REG_RES_RXW32(bar_, reg_, mask_, value_) \
 337         REG_SCRIPT_RES(RXW, 32, bar_, reg_, mask_, value_, 0)
 338 #define REG_RES_OR8(bar_, reg_, value_) \
 339         REG_RES_RMW8(bar_, reg_, 0xff, value_)
 340 #define REG_RES_OR16(bar_, reg_, value_) \
 341         REG_RES_RMW16(bar_, reg_, 0xffff, value_)
 342 #define REG_RES_OR32(bar_, reg_, value_) \
 343         REG_RES_RMW32(bar_, reg_, 0xffffffff, value_)
 344 #define REG_RES_POLL8(bar_, reg_, mask_, value_, timeout_) \
 345         REG_SCRIPT_RES(POLL, 8, bar_, reg_, mask_, value_, timeout_)
 346 #define REG_RES_POLL16(bar_, reg_, mask_, value_, timeout_) \
 347         REG_SCRIPT_RES(POLL, 16, bar_, reg_, mask_, value_, timeout_)
 348 #define REG_RES_POLL32(bar_, reg_, mask_, value_, timeout_) \
 349         REG_SCRIPT_RES(POLL, 32, bar_, reg_, mask_, value_, timeout_)
 350 #define REG_RES_XOR8(bar_, reg_, value_) \
 351         REG_RES_RXW8(bar_, reg_, 0xff, value_)
 352 #define REG_RES_XOR16(bar_, reg_, value_) \
 353         REG_RES_RXW16(bar_, reg_, 0xffff, value_)
 354 #define REG_RES_XOR32(bar_, reg_, value_) \
 355         REG_RES_RXW32(bar_, reg_, 0xffffffff, value_)
 356
 357 #if CONFIG(SOC_INTEL_BAYTRAIL)
 358 /*
 359  * IO Sideband Function
 360  */
 361
 362 #define REG_SCRIPT_IOSF(cmd_, unit_, reg_, mask_, value_, timeout_) \
 363         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,      \
 364                                REG_SCRIPT_TYPE_IOSF,           \
 365                                REG_SCRIPT_SIZE_32,             \
 366                                reg_, mask_, value_, timeout_, unit_)
 367 #define REG_IOSF_READ(unit_, reg_) \
 368         REG_SCRIPT_IOSF(READ, unit_, reg_, 0, 0, 0)
 369 #define REG_IOSF_WRITE(unit_, reg_, value_) \
 370         REG_SCRIPT_IOSF(WRITE, unit_, reg_, 0, value_, 0)
 371 #define REG_IOSF_RMW(unit_, reg_, mask_, value_) \
 372         REG_SCRIPT_IOSF(RMW, unit_, reg_, mask_, value_, 0)
 373 #define REG_IOSF_RXW(unit_, reg_, mask_, value_) \
 374         REG_SCRIPT_IOSF(RXW, unit_, reg_, mask_, value_, 0)
 375 #define REG_IOSF_OR(unit_, reg_, value_) \
 376         REG_IOSF_RMW(unit_, reg_, 0xffffffff, value_)
 377 #define REG_IOSF_POLL(unit_, reg_, mask_, value_, timeout_) \
 378         REG_SCRIPT_IOSF(POLL, unit_, reg_, mask_, value_, timeout_)
 379 #define REG_IOSF_XOR(unit_, reg_, value_) \
 380         REG_IOSF_RXW(unit_, reg_, 0xffffffff, value_)
 381 #endif  /* CONFIG_SOC_INTEL_BAYTRAIL */
 382
 383 /*
 384  * CPU Model Specific Register
 385  */
 386
 387 #define REG_SCRIPT_MSR(cmd_, reg_, mask_, value_, timeout_) \
 388         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_##cmd_,   \
 389                                REG_SCRIPT_TYPE_MSR,         \
 390                                REG_SCRIPT_SIZE_64,          \
 391                                reg_, mask_, value_, timeout_, 0)
 392 #define REG_MSR_READ(reg_) \
 393         REG_SCRIPT_MSR(READ, reg_, 0, 0, 0)
 394 #define REG_MSR_WRITE(reg_, value_) \
 395         REG_SCRIPT_MSR(WRITE, reg_, 0, value_, 0)
 396 #define REG_MSR_RMW(reg_, mask_, value_) \
 397         REG_SCRIPT_MSR(RMW, reg_, mask_, value_, 0)
 398 #define REG_MSR_RXW(reg_, mask_, value_) \
 399         REG_SCRIPT_MSR(RXW, reg_, mask_, value_, 0)
 400 #define REG_MSR_OR(reg_, value_) \
 401         REG_MSR_RMW(reg_, -1ULL, value_)
 402 #define REG_MSR_POLL(reg_, mask_, value_, timeout_) \
 403         REG_SCRIPT_MSR(POLL, reg_, mask_, value_, timeout_)
 404 #define REG_MSR_XOR(reg_, value_) \
 405         REG_MSR_RXW(reg_, -1ULL, value_)
 406
 407 /*
 408  * Chain to another table.
 409  */
 410 #define REG_SCRIPT_NEXT(next_)                \
 411         { .command = REG_SCRIPT_COMMAND_NEXT, \
 412           .next = next_,                      \
 413         }
 414
 415 /*
 416  * Set current device
 417  */
 418 #define REG_SCRIPT_SET_DEV(dev_)                 \
 419         { .command = REG_SCRIPT_COMMAND_SET_DEV, \
 420           .dev = dev_,                           \
 421         }
 422
 423 /*
 424  * Last script entry. All tables need to end with REG_SCRIPT_END.
 425  */
 426 #define REG_SCRIPT_END \
 427         _REG_SCRIPT_ENCODE_RAW(REG_SCRIPT_COMMAND_END, 0, 0, 0, 0, 0, 0, 0)
 428
 429 void reg_script_run(const struct reg_script *script);
 430 #ifdef __SIMPLE_DEVICE__
 431 void reg_script_run_on_dev(pci_devfn_t dev, const struct reg_script *step);
 432 #else
 433 void reg_script_run_on_dev(struct device *dev, const struct reg_script *step);
 434 #endif
 435
 436 #endif /* REG_SCRIPT_H */