1 # Lenovo Ivy Bridge series
3 This information is valid for all supported models, except T430s, [T431s](t431s.md) and [X230s](x230s.md).
7 +---------------------+--------------------------------+
9 +=====================+================================+
10 | Socketed flash | no |
11 +---------------------+--------------------------------+
12 | Size | 8 MiB + 4MiB |
13 +---------------------+--------------------------------+
14 | In circuit flashing | Yes |
15 +---------------------+--------------------------------+
17 +---------------------+--------------------------------+
18 | Write protection | No |
19 +---------------------+--------------------------------+
20 | Dual BIOS feature | No |
21 +---------------------+--------------------------------+
22 | Internal flashing | Yes |
23 +---------------------+--------------------------------+
26 ## Installation instructions
27 * Update the EC firmware, as there's no support for EC updates in coreboot.
28 * Do **NOT** accidentally swap pins or power on the board while a SPI flasher
29 is connected. It will permanently brick your device.
30 * It's recommended to only flash the BIOS region. In that case you don't
31 need to extract blobs from vendor firmware.
32 If you want to flash the whole chip, you need blobs when building
34 * The *Flash layout* shows that by default 7MiB of space are available for
35 the use with coreboot.
36 * In that case you only want to use a part of the BIOS region that must not
37 exceed 4MiB in size, which means CONFIG_CBFS_SIZE must be smaller than 4MiB.
38 * ROM chip size should be set to 12MiB.
41 Please also have a look at :doc:`../../tutorial/flashing_firmware/index`.
44 ## Splitting the coreboot.rom
46 To split the coreboot.rom into two images (one for the 8MiB and one for the
47 4 MiB flash IC), run the following commands:
50 dd of=top.rom bs=1M if=build/coreboot.rom skip=8
51 dd of=bottom.rom bs=1M if=build/coreboot.rom count=8
54 That gives one ROM for each flash IC, where *top.rom* is the upper part of the
55 flash image, that resides on the 4 MiB flash and *bottom.rom* is the lower part
56 of the flash image, that resides on the 8 MiB flash.
60 If you flash externally you need to read both flash chips to get two images
61 (one for the 8MiB and one for the 4 MiB flash IC), and then run the following
62 command to concatenate the files:
65 cat bottom.rom top.rom > firmware.rom
69 There's one 8MiB and one 4 MiB flash which contains IFD, GBE, ME and
70 BIOS region. These two flash ICs appear as a single 12MiB when flashing
72 On Lenovo's UEFI the EC firmware update is placed at the start of the BIOS
73 region. The update is then written into the EC once.
77 [fl]: flashlayout_Ivy_Bridge.svg
79 ## Reducing Intel Management Engine firmware size
81 It is possible to reduce the Intel ME firmware size to free additional
82 space for the `bios` region. This is usually referred to as *cleaning the ME* or
84 After reducing the Intel ME firmware size you must modify the original IFD,
85 [split the resulting coreboot ROM](#splitting-the-coreboot-rom) and then write
86 each ROM using an [external programmer].
87 Have a look at [me_cleaner] for more information.
89 Tests on Lenovo W530 showed no issues with a stripped and shrunken ME firmware.
92 [me_cleaner]: ../../northbridge/intel/sandybridge/me_cleaner.md
93 [external programmer]: ../../tutorial/flashing_firmware/index.md