src/mainboard/51nb/x210/devicetree.cb

   1 chip soc/intel/skylake
   2
   3         # Enable Panel as eDP and configure power delays
   4         register "panel_cfg" = "{
   5                 .up_delay_ms            =  210, // T3
   6                 .down_delay_ms          =  500, // T10
   7                 .cycle_delay_ms         = 5000, // T12
   8                 .backlight_on_delay_ms  =    1, // T7
   9                 .backlight_off_delay_ms =  200, // T9
  10         }"
  11
  12         # Enable deep Sx states
  13         register "deep_s3_enable_ac" = "1"
  14         register "deep_s3_enable_dc" = "1"
  15         register "deep_s5_enable_ac" = "1"
  16         register "deep_s5_enable_dc" = "1"
  17         register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
  18
  19         register "eist_enable" = "true"
  20
  21         # GPE configuration
  22         # Note that GPE events called out in ASL code rely on this
  23         # route. i.e. If this route changes then the affected GPE
  24         # offset bits also need to be changed.
  25         register "gpe0_dw0" = "GPP_C"
  26         register "gpe0_dw1" = "GPP_D"
  27         register "gpe0_dw2" = "GPP_E"
  28
  29         # Disable DPTF
  30         register "dptf_enable" = "0"
  31
  32         # FSP Configuration
  33         register "DspEnable" = "0"
  34         register "IoBufferOwnership" = "0"
  35         register "SkipExtGfxScan" = "1"
  36         register "SaGv" = "SaGv_Enabled"
  37         register "PmConfigSlpS3MinAssert" = "2"         # 50ms
  38         register "PmConfigSlpS4MinAssert" = "1"         # 1s
  39         register "PmConfigSlpSusMinAssert" = "3"        # 500ms
  40         register "PmConfigSlpAMinAssert" = "3"          # 2s
  41
  42         # PL1 override 25W
  43         # PL2 override 44W
  44         register "power_limits_config" = "{
  45                 .tdp_pl1_override = 25,
  46                 .tdp_pl2_override = 44,
  47         }"
  48
  49         # Send an extra VR mailbox command for the PS4 exit issue
  50         register "SendVrMbxCmd" = "2"
  51
  52         device domain 0 on
  53                 device ref igpu         on  end
  54                 device ref sa_thermal   on  end
  55                 device ref south_xhci   on
  56                         register "usb2_ports" = "{
  57                                 [0] = USB2_PORT_MID(OC1),       // Type-A Port (left)
  58                                 [1] = USB2_PORT_MID(OC1),       // Type-A Port (left)
  59                                 [2] = USB2_PORT_FLEX(OC_SKIP),  // FPR
  60                                 [3] = USB2_PORT_FLEX(OC_SKIP),  // SD
  61                                 [4] = USB2_PORT_FLEX(OC_SKIP),  // INT
  62                                 [5] = USB2_PORT_MID(OC1),       // Type-A Port (right)
  63                                 [6] = USB2_PORT_FLEX(OC_SKIP),  // Webcam
  64                                 [7] = USB2_PORT_MID(OC_SKIP),   // mPCIe / WiFi Port
  65                                 [8] = USB2_PORT_MID(OC_SKIP),   // mSATA / WWAN Port
  66                         }"
  67
  68                         register "usb3_ports" = "{
  69                                 [0] = USB3_PORT_DEFAULT(OC1),   // Type-A Port (left)
  70                                 [1] = USB3_PORT_DEFAULT(OC1),   // Type-A Port (left)
  71                         }"
  72                 end
  73                 device ref thermal      on  end
  74                 device ref heci1        on  end
  75                 device ref sata         on
  76                         register "SataSalpSupport" = "1"
  77
  78                         # The X210 has 3 SATA ports: a full SATA port, mSATA, and SATA over M.2
  79                         register "SataPortsEnable" = "{
  80                                 [0] = 1,
  81                                 [1] = 1,
  82                                 [2] = 1,
  83                         }"
  84                         register "SataPortsDevSlp" = "{
  85                                 [0] = 1,
  86                                 [1] = 1,
  87                                 [2] = 1,
  88                         }"
  89                 end
  90                 device ref pcie_rp3     on
  91                         # Ethernet controller
  92                         register "PcieRpEnable[2]" = "1"
  93                         register "PcieRpClkReqSupport[2]" = "1"
  94                         register "PcieRpClkReqNumber[2]" = "0"
  95                         register "PcieRpClkSrcNumber[2]" = "0"
  96                         register "PcieRpAdvancedErrorReporting[2]" = "1"
  97                         register "PcieRpLtrEnable[2]" = "1"
  98                 end
  99                 device ref pcie_rp4     on
 100                         # Wireless controller
 101                         register "PcieRpEnable[3]" = "1"
 102                         register "PcieRpClkReqSupport[3]" = "1"
 103                         register "PcieRpClkReqNumber[3]" = "1"
 104                         register "PcieRpClkSrcNumber[3]" = "1"
 105                         register "PcieRpAdvancedErrorReporting[3]" = "1"
 106                         register "PcieRpLtrEnable[3]" = "1"
 107                 end
 108                 device ref pcie_rp9     on
 109                         # NVMe controller
 110                         register "PcieRpEnable[8]" = "1"
 111                         register "PcieRpClkReqSupport[8]" = "1"
 112                         register "PcieRpClkReqNumber[8]" = "4"
 113                         register "PcieRpClkSrcNumber[8]" = "4"
 114                         register "PcieRpAdvancedErrorReporting[8]" = "1"
 115                         register "PcieRpLtrEnable[8]" = "1"
 116                 end
 117                 device ref lpc_espi     on
 118                         register "serirq_mode" = "SERIRQ_CONTINUOUS"
 119
 120                         register "gen1_dec" = "0x000c0681"
 121                         register "gen2_dec" = "0x000c1641"
 122
 123                         chip ec/51nb/npce985la0dx
 124                                 device pnp 0c09.0 on end
 125                                 device pnp 4e.5   on end
 126                                 device pnp 4e.6   on end
 127                                 device pnp 4e.11  on end
 128                         end
 129                 end
 130                 device ref pmc          on  end
 131                 device ref hda          on  end
 132                 device ref smbus        on  end
 133         end
 134 end