src/mainboard/amd/pademelon/bootblock/bootblock.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <soc/southbridge.h>
   5 #include <amdblocks/lpc.h>
   6 #include <device/pci_ops.h>
   7 #include <gpio.h>
   8 #include <soc/pci_devs.h>
   9 #include <drivers/uart/uart8250reg.h>
  10 #include <arch/io.h>
  11 #include "../gpio.h"
  12
  13 /* Enable IO access to port, then enable UART HW control pins */
  14 static void enable_serial(unsigned int base_port, unsigned int io_enable)
  15 {
  16         u8 reg;
  17
  18         pci_or_config32(SOC_LPC_DEV, LPC_IO_PORT_DECODE_ENABLE, io_enable);
  19
  20         /*
  21          * Remove this section if HW handshake is not needed. This is needed
  22          * only for those who don't have a modified serial cable (connecting
  23          * DCD to DTR and DSR, plus connecting RTS to CTS). When you buy cables
  24          * on any store, they don't have these modification.
  25          */
  26         reg = inb(base_port + UART8250_MCR);
  27         reg |= UART8250_MCR_DTR | UART8250_MCR_RTS;
  28         outb(reg, base_port + UART8250_MCR);
  29 }
  30
  31 void bootblock_mainboard_early_init(void)
  32 {
  33         fch_clk_output_48Mhz(2);
  34         /*
  35          * UARTs enabled by default at reset, just need RTS, CTS
  36          * and access to the IO address.
  37          */
  38         enable_serial(0x03f8, DECODE_ENABLE_SERIAL_PORT0);
  39         enable_serial(0x02f8, DECODE_ENABLE_SERIAL_PORT1);
  40 }
  41
  42 void bootblock_mainboard_init(void)
  43 {
  44         size_t num_gpios;
  45         const struct soc_amd_gpio *gpios;
  46
  47         gpios = early_gpio_table(&num_gpios);
  48         gpio_configure_pads(gpios, num_gpios);
  49 }