src/mainboard/cwwk/adl/devicetree.cb

   1 chip soc/intel/alderlake
   2
   3         register "s0ix_enable" = "true"
   4
   5         register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)"
   6         register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)"
   7         register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)"
   8         register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)"
   9         register "usb2_ports[4]" = "USB2_PORT_SHORT(OC_SKIP)"
  10         register "usb2_ports[5]" = "USB2_PORT_SHORT(OC_SKIP)"
  11         register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # microSD card reader
  12         register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)"
  13
  14         register "pch_pcie_rp[PCH_RP(1)]" = "{
  15                 .clk_src = 0,
  16                 .clk_req = 0,
  17                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
  18         }"
  19
  20         register "pch_pcie_rp[PCH_RP(7)]" = "{
  21                 .clk_src = 1,
  22                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
  23                 .pcie_rp_aspm = ASPM_DISABLE,
  24         }"
  25
  26         register "pch_pcie_rp[PCH_RP(9)]" = "{
  27                 .clk_src = 2,
  28                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
  29                 .pcie_rp_aspm = ASPM_DISABLE,
  30         }"
  31
  32         register "pch_pcie_rp[PCH_RP(10)]" = "{
  33                 .clk_src = 3,
  34                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
  35                 .pcie_rp_aspm = ASPM_DISABLE,
  36         }"
  37
  38         register "pch_pcie_rp[PCH_RP(11)]" = "{
  39                 .clk_src = 4,
  40                 .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN,
  41                 .pcie_rp_aspm = ASPM_DISABLE,
  42         }"
  43
  44         register "pch_pcie_rp[PCH_RP(12)]" = "{
  45                 .clk_src = 5,
  46                 .clk_req = 5,
  47                 .flags = PCIE_RP_LTR | PCIE_RP_AER,
  48         }"
  49
  50         # Enable EDP in PortA
  51         register "ddi_portA_config" = "1"
  52
  53         device domain 0 on
  54                 device ref igpu on end
  55                 device ref dtt on end
  56                 device ref crashlog off end
  57                 device ref xhci on end
  58                 device ref shared_sram on end
  59                 device ref pcie_rp1 on end
  60                 device ref pcie_rp7 on end
  61                 device ref pcie_rp9 on end
  62                 device ref pcie_rp10 on end
  63                 device ref pcie_rp11 on end
  64                 device ref pcie_rp12 on end # M.2 E key port
  65                 device ref pch_espi on
  66                         chip superio/ite/it8613e
  67                                 device pnp 2e.0 off end
  68                                 device pnp 2e.1 on      # COM 1
  69                                         io 0x60 = 0x3f8
  70                                         irq 0x70 = 0x4
  71                                         irq 0xf0 = 0x1
  72                                 end
  73                                 device pnp 2e.4 off end # Environment Controller
  74                                 device pnp 2e.5 off end # Keyboard
  75                                 device pnp 2e.6 off end # Mouse
  76                                 device pnp 2e.7 off end # GPIO
  77                                 device pnp 2e.a off end # CIR
  78                         end
  79                 end
  80                 device ref hda on end
  81                 device ref smbus on end
  82         end
  83 end