src/mainboard/getac/p470/early_init.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <bootblock_common.h>
   4 #include <stdint.h>
   5 #include <arch/io.h>
   6 #include <device/pnp_ops.h>
   7 #include <device/pci_ops.h>
   8 #include <option.h>
   9 #include <console/console.h>
  10 #include <northbridge/intel/i945/i945.h>
  11 #include <southbridge/intel/i82801gx/i82801gx.h>
  12
  13 void mainboard_pre_raminit_config(int s3_resume)
  14 {
  15         u32 gpios;
  16
  17         printk(BIOS_SPEW, "\n  Initializing drive bay...\n");
  18         gpios = inl(DEFAULT_GPIOBASE + 0x38); // GPIO Level 2
  19         gpios |= (1 << 0); // GPIO33 = ODD
  20         gpios |= (1 << 1); // GPIO34 = IDE_RST#
  21         outl(gpios, DEFAULT_GPIOBASE + 0x38);   /* GP_LVL2 */
  22
  23         gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
  24         gpios &= ~(1 << 13);    // ??
  25         outl(gpios, DEFAULT_GPIOBASE + 0x0c);   /* GP_LVL */
  26
  27         printk(BIOS_SPEW, "\n  Initializing Ethernet NIC...\n");
  28         gpios = inl(DEFAULT_GPIOBASE + 0x0c); // GPIO Level
  29         gpios &= ~(1 << 24);    // Enable LAN Power
  30         outl(gpios, DEFAULT_GPIOBASE + 0x0c);   /* GP_LVL */
  31 }
  32
  33 /* Override the default lpc decode ranges */
  34 void mainboard_lpc_decode(void)
  35 {
  36         int lpt_en = 0;
  37
  38         if (get_uint_option("lpt", 0))
  39                 lpt_en = LPT_LPC_EN; /* enable LPT */
  40
  41         // decode range
  42         pci_write_config16(PCI_DEV(0, 0x1f, 0), LPC_IO_DEC, 0x0007);
  43         // decode range
  44         pci_update_config32(PCI_DEV(0, 0x1f, 0), LPC_EN, ~LPT_LPC_EN, lpt_en);
  45 }
  46
  47 /* This box has two superios, so enabling serial becomes slightly excessive.
  48  * We disable a lot of stuff to make sure that there are no conflicts between
  49  * the two. Also set up the GPIOs from the beginning. This is the "no schematic
  50  * but safe anyways" method.
  51  */
  52 static void pnp_enter_ext_func_mode(pnp_devfn_t dev)
  53 {
  54         unsigned int port = dev >> 8;
  55         outb(0x55, port);
  56 }
  57
  58 static void pnp_exit_ext_func_mode(pnp_devfn_t dev)
  59 {
  60         unsigned int port = dev >> 8;
  61         outb(0xaa, port);
  62 }
  63
  64 void bootblock_mainboard_early_init(void)
  65 {
  66         const pnp_devfn_t dev = PNP_DEV(0x4e, 0x00);
  67
  68         pnp_enter_ext_func_mode(dev);
  69         pnp_write_config(dev, 0x02, 0x0e); // UART power
  70         pnp_write_config(dev, 0x1b, (0x3e8 >> 2)); // UART3 base
  71         pnp_write_config(dev, 0x1c, (0x2e8 >> 2)); // UART4 base
  72         pnp_write_config(dev, 0x1d, (5 << 4) | 11); // UART3,4 IRQ
  73         pnp_write_config(dev, 0x1e, 1); // no 32khz clock
  74         pnp_write_config(dev, 0x24, (0x3f8 >> 2)); // UART1 base
  75         pnp_write_config(dev, 0x28, (4 << 4) | 0); // UART1,2 IRQ
  76         pnp_write_config(dev, 0x2c, 0); // DMA0 FIR
  77         pnp_write_config(dev, 0x30, (0x600 >> 4)); // Runtime Register Block Base
  78
  79         pnp_write_config(dev, 0x31, 0xce); // GPIO1 DIR
  80         pnp_write_config(dev, 0x32, 0x00); // GPIO1 POL
  81         pnp_write_config(dev, 0x33, 0x0f); // GPIO2 DIR
  82         pnp_write_config(dev, 0x34, 0x00); // GPIO2 POL
  83         pnp_write_config(dev, 0x35, 0xa8); // GPIO3 DIR
  84         pnp_write_config(dev, 0x36, 0x00); // GPIO3 POL
  85         pnp_write_config(dev, 0x37, 0xa8); // GPIO4 DIR
  86         pnp_write_config(dev, 0x38, 0x00); // GPIO4 POL
  87
  88         pnp_write_config(dev, 0x39, 0x00); // GPIO1 OUT
  89         pnp_write_config(dev, 0x40, 0x80); // GPIO2/MISC OUT
  90         pnp_write_config(dev, 0x41, 0x00); // GPIO5 OUT
  91         pnp_write_config(dev, 0x42, 0xa8); // GPIO5 DIR
  92         pnp_write_config(dev, 0x43, 0x00); // GPIO5 POL
  93         pnp_write_config(dev, 0x44, 0x00); // GPIO ALT1
  94         pnp_write_config(dev, 0x45, 0x50); // GPIO ALT2
  95         pnp_write_config(dev, 0x46, 0x00); // GPIO ALT3
  96
  97         pnp_write_config(dev, 0x48, 0x55); // GPIO ALT5
  98         pnp_write_config(dev, 0x49, 0x55); // GPIO ALT6
  99         pnp_write_config(dev, 0x4a, 0x55); // GPIO ALT7
 100         pnp_write_config(dev, 0x4b, 0x55); // GPIO ALT8
 101         pnp_write_config(dev, 0x4c, 0x55); // GPIO ALT9
 102         pnp_write_config(dev, 0x4d, 0x55); // GPIO ALT10
 103
 104         pnp_exit_ext_func_mode(dev);
 105 }
 106
 107 void mainboard_late_rcba_config(void)
 108 {
 109         /* Device 1f interrupt pin register */
 110         RCBA32(D31IP) = 0x00042220;
 111         /* Device 1d interrupt pin register */
 112         RCBA32(D28IP) = 0x00214321;
 113
 114         /* dev irq route register */
 115         RCBA16(D31IR) = 0x0232;
 116         RCBA16(D30IR) = 0x3246;
 117         RCBA16(D29IR) = 0x0237;
 118         RCBA16(D28IR) = 0x3201;
 119         RCBA16(D27IR) = 0x3216;
 120
 121         /* Disable unused devices */
 122         RCBA32(FD) |= FD_INTLAN;
 123
 124         /* This should probably go into the ACPI enable trap */
 125
 126         /* Set up I/O Trap #3 for 0x800-0x80c (Trap) */
 127         RCBA32(0x1e9c) = 0x000200f0;
 128         RCBA32(0x1e98) = 0x000c0801;
 129 }