src/mainboard/google/auron/smihandler.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <cpu/x86/smm.h>
   5 #include <soc/pm.h>
   6 #include <ec/google/chromeec/ec.h>
   7 #include <ec/google/chromeec/smm.h>
   8 #include <southbridge/intel/lynxpoint/lp_gpio.h>
   9 #include <soc/iomap.h>
  10 #include "ec.h"
  11 #include <variant/onboard.h>
  12
  13 /* gpi_sts is GPIO 47:32 */
  14 void mainboard_smi_gpi(u32 gpi_sts)
  15 {
  16         if (gpi_sts & (1 << (EC_SMI_GPI - 32)))
  17                 chromeec_smi_process_events();
  18 }
  19
  20 static void mainboard_disable_gpios(void)
  21 {
  22 #if CONFIG(BOARD_GOOGLE_SAMUS)
  23         /* Put SSD in reset to prevent leak */
  24         set_gpio(BOARD_SSD_RESET_GPIO, 0);
  25         /* Disable LTE */
  26         set_gpio(BOARD_LTE_DISABLE_GPIO, 0);
  27 #else
  28         set_gpio(BOARD_PP3300_CODEC_GPIO, 0);
  29 #endif
  30         /* Prevent leak from standby rail to WLAN rail */
  31         set_gpio(BOARD_WLAN_DISABLE_GPIO, 0);
  32 }
  33
  34 void mainboard_smi_sleep(u8 slp_typ)
  35 {
  36         /* Disable USB charging if required */
  37         /* NOTE: Setting of usb0 _may_ also control usb1 here. */
  38         chromeec_set_usb_charge_mode(slp_typ);
  39
  40         switch (slp_typ) {
  41         case ACPI_S3:
  42         case ACPI_S5:
  43                 mainboard_disable_gpios();
  44                 break;
  45         }
  46
  47         chromeec_smi_sleep(slp_typ, MAINBOARD_EC_S3_WAKE_EVENTS, MAINBOARD_EC_S5_WAKE_EVENTS);
  48 }
  49
  50 int mainboard_smi_apmc(u8 apmc)
  51 {
  52         chromeec_smi_apmc(apmc, MAINBOARD_EC_SCI_EVENTS, MAINBOARD_EC_SMI_EVENTS);
  53         return 0;
  54 }