src/mainboard/google/brya/chromeos.fmd

   1 FLASH 32M {
   2         SI_ALL 5M {
   3                 SI_DESC 4K
   4                 SI_ME {
   5                         CSE_LAYOUT 8K
   6                         CSE_RO 1640K
   7                         CSE_DATA 420K
   8                         # 64-KiB aligned to optimize RW erases during CSE update.
   9                         CSE_RW 3008K
  10                 }
  11         }
  12         SI_BIOS 27M {
  13                 RW_SECTION_A 8M {
  14                         VBLOCK_A 64K
  15                         FW_MAIN_A(CBFS)
  16                         RW_FWID_A 64
  17                 }
  18                 RW_LEGACY(CBFS) 2M
  19                 RW_MISC 1M {
  20                         UNIFIED_MRC_CACHE(PRESERVE) 128K {
  21                                 RECOVERY_MRC_CACHE 64K
  22                                 RW_MRC_CACHE 64K
  23                         }
  24                         RW_ELOG(PRESERVE) 16K
  25                         RW_SHARED 16K {
  26                                 SHARED_DATA 8K
  27                                 VBLOCK_DEV 8K
  28                         }
  29                         # The RW_SPD_CACHE region is only used for brya variants that use DDRx memory.
  30                         # It is placed in the common `chromeos.fmd` file because it is only 4K and there
  31                         # is free space in the RW_MISC region that cannot be easily reclaimed because
  32                         # the RW_SECTION_B must start on the 16M boundary.
  33                         RW_SPD_CACHE(PRESERVE) 4K
  34                         RW_VPD(PRESERVE) 8K
  35                         RW_NVRAM(PRESERVE) 24K
  36                 }
  37                 # This section starts at the 16M boundary in SPI flash.
  38                 # ADL does not support a region crossing this boundary,
  39                 # because the SPI flash is memory-mapped into two non-
  40                 # contiguous windows.
  41                 RW_SECTION_B 8M {
  42                         VBLOCK_B 64K
  43                         FW_MAIN_B(CBFS)
  44                         RW_FWID_B 64
  45                 }
  46                 # Make WP_RO region align with SPI vendor
  47                 # memory protected range specification.
  48                 WP_RO 8M {
  49                         RO_VPD(PRESERVE) 16K
  50 #if CONFIG_TPM_GOOGLE_TI50
  51                         RO_GSCVD 8K
  52 #endif
  53                         RO_SECTION {
  54                                 FMAP 2K
  55                                 RO_FRID 64
  56                                 GBB@4K 448K
  57                                 COREBOOT(CBFS)
  58                         }
  59                 }
  60         }
  61 }