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mainboard/intel/avenuecity_crb: Update full IIO configuration
[coreboot2.git] / src / mainboard / google / dedede / variants / baseboard / devicetree.cb
blobcc2b66d6d9ba14180ab27e412ea7a0faad2cda57
1 fw_config
2 field DB_PORTS 0 3
3 option DB_PORTS_NONE 0
4 option DB_PORTS_2C_2A 1
5 option DB_PORTS_1C_LTE 2
6 option DB_PORTS_1A_HDMI 3
7 option DB_PORTS_1C_1A 4
8 option DB_PORTS_LTE_HDMI 5
9 option DB_PORTS_1C_1A_LTE 6
10 option DB_PORTS_1C 7
11 option DB_PORTS_1A_HDMI_LTE 8
12 option DB_PORTS_LTE 9
13 end
14 field STYLUS 4
15 option STYLUS_ABSENT 0
16 option STYLUS_PRESENT 1
17 end
18 field TOUCHSCREEN 5
19 option TOUCHSCREEN_ABSENT 0
20 option TOUCHSCREEN_PRESENT 1
21 end
22 field TABLETMODE 10
23 option TABLETMODE_DISABLED 0
24 option TABLETMODE_ENABLED 1
25 end
26 field LTE 11
27 option LTE_ABSENT 0
28 option LTE_PRESENT 1
29 end
30 field AUDIO_AMP 14 16
31 option UNPROVISIONED 0
32 option MAX98360 1
33 option RT1015_I2C 2
34 option RT1015P_AUTO 3
35 option ALC5650 4
36 end
37 field EXT_VR 18
38 option EXT_VR_PRESENT 0
39 option EXT_VR_ABSENT 1
40 end
41 end
42
43 chip soc/intel/jasperlake
44 device cpu_cluster 0 on end
45
46 # GPE configuration
47 # Note that GPE events called out in ASL code rely on this
48 # route, i.e., if this route changes then the affected GPE
49 # offset bits also need to be changed.
50 # DW0 is used by:
51 # - GPP_B3 - TRACKPAD_INT_ODL
52 # - GPP_B4 - H1_AP_INT_ODL
53 # DW1 is used by:
54 # - GPP_C12 - AP_PEN_DET_ODL
55 # DW2 is used by:
56 # - GPP_D0 - WWAN_HOST_WAKE
57 # - GPP_D3 - WLAN_PCIE_WAKE_ODL
58 # EC_AP_WAKE_ODL is routed to LAN_WAKE#/GPD02 & is part of DW3.
59 register "pmc_gpe0_dw0" = "PMC_GPP_B"
60 register "pmc_gpe0_dw1" = "PMC_GPP_C"
61 register "pmc_gpe0_dw2" = "PMC_GPP_D"
62
63 # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
64 register "gen1_dec" = "0x00fc0801"
65 register "gen2_dec" = "0x000c0201"
66 # EC memory map range is 0x900-0x9ff
67 register "gen3_dec" = "0x00fc0901"
68
69 # USB Port Configuration
70 register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C0
71 register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-C Port C1
72 register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0
73 register "usb2_ports[3]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A1
74 register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth
75 register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Integrated Bluetooth
76
77 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C0
78 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/2 Type-C Port C1
79 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A0
80 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3/1 Type-A Port A1
81
82 register "SerialIoI2cMode" = "{
83 [PchSerialIoIndexI2C0] = PchSerialIoPci,
84 [PchSerialIoIndexI2C1] = PchSerialIoPci,
85 [PchSerialIoIndexI2C2] = PchSerialIoPci,
86 [PchSerialIoIndexI2C3] = PchSerialIoPci,
87 [PchSerialIoIndexI2C4] = PchSerialIoPci,
88 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
89 }"
90
91 register "SerialIoGSpiMode" = "{
92 [PchSerialIoIndexGSPI0] = PchSerialIoPci,
93 [PchSerialIoIndexGSPI1] = PchSerialIoDisabled,
94 [PchSerialIoIndexGSPI2] = PchSerialIoDisabled,
95 }"
96
97 register "SerialIoGSpiCsMode" = "{
98 [PchSerialIoIndexGSPI0] = 1,
99 [PchSerialIoIndexGSPI1] = 0,
100 [PchSerialIoIndexGSPI2] = 0,
101 }"
102
103 register "SerialIoGSpiCsState" = "{
104 [PchSerialIoIndexGSPI0] = 0,
105 [PchSerialIoIndexGSPI1] = 0,
106 [PchSerialIoIndexGSPI2] = 0,
107 }"
108
109 register "SerialIoUartMode" = "{
110 [PchSerialIoIndexUART0] = PchSerialIoDisabled,
111 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
112 [PchSerialIoIndexUART2] = PchSerialIoSkipInit,
113 }"
114
115 register "PcieClkSrcUsage[0]" = "0xff"
116 register "PcieClkSrcUsage[1]" = "0xff"
117 register "PcieClkSrcUsage[2]" = "0xff"
118 # PCIe Clock Source 4 (index 3) is used by WLAN on PCIe Root Port 8 (index 7)
119 register "PcieClkSrcUsage[3]" = "7"
120 register "PcieClkSrcUsage[4]" = "0xff"
121 register "PcieClkSrcUsage[5]" = "0xff"
122
123 # PCIE Clock Request to Clock Source Mapping
124 register "PcieClkSrcClkReq[0]" = "0"
125 register "PcieClkSrcClkReq[1]" = "1"
126 register "PcieClkSrcClkReq[2]" = "2"
127 register "PcieClkSrcClkReq[3]" = "3"
128 register "PcieClkSrcClkReq[4]" = "4"
129 register "PcieClkSrcClkReq[5]" = "5"
130
131 # Audio related configurations
132 register "PchHdaDspEnable" = "1"
133 register "PchHdaAudioLinkHdaEnable" = "1"
134 register "PchHdaAudioLinkSspEnable[0]" = "1"
135 register "PchHdaAudioLinkSspEnable[1]" = "1"
136 register "PchHdaAudioLinkDmicEnable[0]" = "1"
137 register "PchHdaAudioLinkDmicEnable[1]" = "1"
138
139 # Enable EMMC HS400 mode
140 register "ScsEmmcHs400Enabled" = "1"
141
142 # GPIO for SD card detect
143 register "sdcard_cd_gpio" = "VGPIO_39"
144 # SD card power enable polarity
145 register "SdCardPowerEnableActiveHigh" = "1"
146
147 # Enable S0ix support
148 register "s0ix_enable" = "true"
149
150 # Display related UPDs
151 # Select eDP for port A
152 register "DdiPortAConfig" = "1"
153
154 # Enable HPD for DDI ports B/C
155 register "DdiPortBHpd" = "1"
156 register "DdiPortCHpd" = "1"
157 # Enable DDC for DDI ports B/C
158 register "DdiPortBDdc" = "1"
159 register "DdiPortCDdc" = "1"
160
161 # Enable DPTF
162 register "dptf_enable" = "1"
163
164 # Power limit config
165 register "power_limits_config[JSL_N4500_6W_CORE]" = "{
166 .tdp_pl1_override = 6,
167 .tdp_pl2_override = 20,
168 }"
169
170 register "power_limits_config[JSL_N6000_6W_CORE]" = "{
171 .tdp_pl1_override = 6,
172 .tdp_pl2_override = 20,
173 }"
174
175 register "power_limits_config[JSL_N5100_6W_CORE]" = "{
176 .tdp_pl1_override = 6,
177 .tdp_pl2_override = 20,
178 }"
179
180 register "power_limits_config[JSL_N4505_10W_CORE]" = "{
181 .tdp_pl1_override = 10,
182 .tdp_pl2_override = 25,
183 }"
184
185 register "power_limits_config[JSL_N5105_10W_CORE]" = "{
186 .tdp_pl1_override = 10,
187 .tdp_pl2_override = 25,
188 }"
189
190 register "power_limits_config[JSL_N6005_10W_CORE]" = "{
191 .tdp_pl1_override = 10,
192 .tdp_pl2_override = 25,
193 }"
194
195 register "tcc_offset" = "10" # TCC of 90C
196
197 # VR config settings
198 # Imon Slope correction specified in 1/100 increment values. Range is 0-200.
199 # Eg: 125 = 1.25
200 register "ImonSlope" = "100"
201
202 # Imon offset correction. Value is a 2's complement signed integer.
203 # Units 1/1000, Range 0-63999.
204 # For an offset = 12.580, use 12580
205 register "ImonOffset" = "0"
206
207 # Skip the CPU replacement check
208 register "SkipCpuReplacementCheck" = "1"
209
210 # Sagv Configuration
211 register "SaGv" = "SaGv_Enabled"
212
213 # Set the minimum assertion width
214 register "PchPmSlpS3MinAssert" = "3" # 50ms
215 register "PchPmSlpS4MinAssert" = "1" # 1s
216 register "PchPmSlpSusMinAssert" = "3" # 1s
217 register "PchPmSlpAMinAssert" = "3" # 98ms
218
219 # NOTE: Duration programmed in the below register should never be smaller than the
220 # stretch duration programmed in the following registers -
221 # - GEN_PMCON_A.SLP_S3_MIN_ASST_WDTH (PchPmSlpS3MinAssert)
222 # - GEN_PMCON_A.S4MAW (PchPmSlpS4MinAssert)
223 # - PM_CFG.SLP_A_MIN_ASST_WDTH (PchPmSlpAMinAssert)
224 # - PM_CFG.SLP_LAN_MIN_ASST_WDTH
225 register "PchPmPwrCycDur" = "1" # 1s
226
227 # Set xHCI LFPS period sampling off time, the default is 9ms.
228 register "xhci_lfps_sampling_offtime_ms" = "9"
229
230 device domain 0 on
231 device pci 00.0 on end # Host Bridge
232 device pci 02.0 on
233 register "gfx" = "GMA_DEFAULT_PANEL(0)"
234 end # Integrated Graphics Device
235 device pci 04.0 on
236 # Default DPTF Policy for all Dedede boards if not overridden
237 chip drivers/intel/dptf
238 ## Passive Policy
239 register "policies.passive" = "{
240 [0] = DPTF_PASSIVE(CPU, CPU, 90, 10000),
241 [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 80, 60000),
242 [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 55, 15000),
243 [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 75, 15000)
244 }"
245
246 ## Critical Policy
247 register "policies.critical" = "{
248 [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN),
249 [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN),
250 [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 80, SHUTDOWN),
251 [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 90, SHUTDOWN)
252 }"
253
254 ## Power Limits Control
255 register "controls.power_limits" = "{
256 .pl1 = {
257 .min_power = 3000,
258 .max_power = 6000,
259 .time_window_min = 1 * MSECS_PER_SEC,
260 .time_window_max = 1 * MSECS_PER_SEC,
261 .granularity = 200,
262 },
263 .pl2 = {
264 .min_power = 20000,
265 .max_power = 20000,
266 .time_window_min = 1 * MSECS_PER_SEC,
267 .time_window_max = 1 * MSECS_PER_SEC,
268 .granularity = 1000,
269 }
270 }"
271
272 register "options.tsr[0].desc" = ""Memory""
273 register "options.tsr[1].desc" = ""Ambient""
274 register "options.tsr[2].desc" = ""Charger""
275
276 ## Charger Performance Control (Control, mA)
277 register "controls.charger_perf" = "{
278 [0] = { 255, 3000 },
279 [1] = { 24, 1500 },
280 [2] = { 16, 1000 },
281 [3] = { 8, 500 }
282 }"
283
284 device generic 0 on end
285 end
286 end # SA Thermal device
287 device pci 05.0 off end # IPU
288 device pci 09.0 off end # Intel Trace Hub
289 device pci 12.6 off end # GSPI 2
290 device pci 14.0 on
291 chip drivers/usb/acpi
292 register "desc" = ""Root Hub""
293 register "type" = "UPC_TYPE_HUB"
294 device usb 0.0 on
295 chip drivers/usb/acpi
296 register "desc" = ""Left Type-C Port""
297 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
298 register "group" = "ACPI_PLD_GROUP(1, 1)"
299 device usb 2.0 on end
300 end
301 chip drivers/usb/acpi
302 register "desc" = ""Right Type-C Port""
303 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
304 register "group" = "ACPI_PLD_GROUP(2, 1)"
305 device usb 2.1 on end
306 end
307 chip drivers/usb/acpi
308 register "desc" = ""Left Type-A Port""
309 register "type" = "UPC_TYPE_A"
310 register "group" = "ACPI_PLD_GROUP(1, 2)"
311 device usb 2.2 on end
312 end
313 chip drivers/usb/acpi
314 register "desc" = ""Right Type-A Port""
315 register "type" = "UPC_TYPE_A"
316 register "group" = "ACPI_PLD_GROUP(2, 2)"
317 device usb 2.3 on end
318 end
319 chip drivers/usb/acpi
320 device usb 2.4 off end
321 end
322 chip drivers/usb/acpi
323 device usb 2.5 off end
324 end
325 chip drivers/usb/acpi
326 device usb 2.6 off end
327 end
328 chip drivers/usb/acpi
329 register "desc" = ""Bluetooth""
330 register "type" = "UPC_TYPE_INTERNAL"
331 register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H19)"
332 device usb 2.7 on end
333 end
334 chip drivers/usb/acpi
335 register "desc" = ""Left Type-C Port""
336 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
337 register "group" = "ACPI_PLD_GROUP(1, 1)"
338 device usb 3.0 on end
339 end
340 chip drivers/usb/acpi
341 register "desc" = ""Right Type-C Port""
342 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
343 register "group" = "ACPI_PLD_GROUP(2, 1)"
344 device usb 3.1 on end
345 end
346 chip drivers/usb/acpi
347 register "desc" = ""Left Type-A Port""
348 register "type" = "UPC_TYPE_USB3_A"
349 register "group" = "ACPI_PLD_GROUP(1, 2)"
350 device usb 3.2 on end
351 end
352 chip drivers/usb/acpi
353 register "desc" = ""Right Type-A Port""
354 register "type" = "UPC_TYPE_USB3_A"
355 register "group" = "ACPI_PLD_GROUP(2, 2)"
356 device usb 3.3 on end
357 end
358 end
359 end
360 end # USB xHCI
361 device pci 14.1 off end # USB xDCI (OTG)
362 device pci 14.2 alias shared_ram on end # PMC SRAM
363 device pci 14.3 on
364 chip drivers/wifi/generic
365 register "wake" = "GPE0_PME_B0"
366 device generic 0 on end
367 end
368 end # CNVi wifi
369 device pci 14.5 on end # SDCard
370 device pci 15.0 on end # I2C 0
371 device pci 15.1 on end # I2C 1
372 device pci 15.2 on end # I2C 2
373 device pci 15.3 on end # I2C 3
374 device pci 16.0 on end # HECI 1
375 device pci 16.1 off end # HECI 2
376 device pci 16.4 off end # HECI 3
377 device pci 16.5 off end # HECI 4
378 device pci 17.0 off end # SATA
379 device pci 19.0 on end # I2C 4
380 device pci 19.1 off end # I2C 5
381 device pci 19.2 on end # UART 2
382 device pci 1a.0 on end # eMMC
383 device pci 1c.0 off end # PCI Express Root Port 1
384 device pci 1c.1 off end # PCI Express Root Port 2
385 device pci 1c.2 off end # PCI Express Root Port 3
386 device pci 1c.3 off end # PCI Express Root Port 4
387 device pci 1c.4 off end # PCI Express Root Port 5
388 device pci 1c.5 off end # PCI Express Root Port 6
389 device pci 1c.6 off end # PCI Express Root Port 7
390 # External PCIe port 4 is mapped to PCIe Root port 8
391 device pci 1c.7 on end # PCI Express Root Port 8 - hosts M.2 E-key WLAN
392 device pci 1e.0 off end # UART 0
393 device pci 1e.1 off end # UART 1
394 device pci 1e.2 on
395 chip drivers/spi/acpi
396 register "hid" = "ACPI_DT_NAMESPACE_HID"
397 register "compat_string" = ""google,cr50""
398 register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_B4_IRQ)"
399 device spi 0 on end
400 end
401 end # GSPI 0
402 device pci 1e.3 off end # GSPI 1
403 device pci 1f.0 on
404 chip ec/google/chromeec
405 device pnp 0c09.0 on end
406 end
407 end # eSPI Interface
408 device pci 1f.1 on end # P2SB
409 device pci 1f.2 hidden end # Power Management Controller
410 device pci 1f.3 on
411 chip drivers/sof
412 register "spkr_tplg" = "rt1015"
413 register "jack_tplg" = "rt5682"
414 register "mic_tplg" = "_2ch_pdm0"
415 device generic 0 on
416 probe AUDIO_AMP RT1015_I2C
417 probe AUDIO_AMP RT1015P_AUTO
418 probe AUDIO_AMP UNPROVISIONED
419 end
420 end
421 chip drivers/sof
422 register "spkr_tplg" = "max98360a"
423 register "jack_tplg" = "rt5682"
424 register "mic_tplg" = "_2ch_pdm0"
425 device generic 0 on
426 probe AUDIO_AMP MAX98360
427 end
428 end
429 end # Intel HDA/cAVS
430 device pci 1f.4 off end # SMBus
431 device pci 1f.5 on end # PCH SPI
432 device pci 1f.7 off end # Intel Trace Hub
433 end
434 end
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