src/mainboard/google/dedede/variants/baseboard/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <types.h>
   6 #include <vendorcode/google/chromeos/chromeos.h>
   7
   8 /* Pad configuration in ramstage */
   9 static const struct pad_config gpio_table[] = {
  10         /* GPP_A0 thru GPP_A6 come configured out of reset, do not touch */
  11         /* A0  : ESPI_IO0 */
  12         /* A1  : ESPI_IO1 */
  13         /* A2  : ESPI_IO2 */
  14         /* A3  : ESPI_IO3 */
  15         /* A4  : ESPI_CS# */
  16         /* A5  : ESPI_CLK */
  17         /* A6  : ESPI_RESET_L */
  18         /* A7  : SMB_CLK */
  19         PAD_NC(GPP_A7, NONE),
  20         /* A8  : SMB_DATA */
  21         PAD_NC(GPP_A8, NONE),
  22         /* A9  : SMB_ALERT_N */
  23         PAD_NC(GPP_A9, NONE),
  24         /* A10 : WWAN_EN */
  25         PAD_NC(GPP_A10, NONE),
  26         /* A11 : TOUCH_RPT_EN */
  27         PAD_CFG_GPO(GPP_A11, 0, DEEP),
  28         /* A12 : USB_OC1_N */
  29         PAD_NC(GPP_A12, NONE),
  30         /* A13 : USB_OC2_N */
  31         PAD_NC(GPP_A13, NONE),
  32         /* A14 : USB_OC3_N */
  33         PAD_NC(GPP_A14, NONE),
  34         /* A15 : GPP_A15 */
  35         PAD_NC(GPP_A15, NONE),
  36         /* A16 : EC_AP_USB_C0_HPD */
  37         PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
  38         /* A17 : EDP_HPD */
  39         PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  40         /* A18 : USB_OC0_N */
  41         PAD_NC(GPP_A18, NONE),
  42         /* A19 : PCHHOT_N */
  43         PAD_NC(GPP_A19, NONE),
  44
  45         /* B0  : VCCIN_AUX_VID0 */
  46         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  47         /* B1  : VCCIN_AUX_VID1 */
  48         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  49         /* B2  : PROCHOT_ODL */
  50         PAD_NC(GPP_B2, NONE),
  51         /* B3  : TRACKPAD_INT_ODL */
  52         PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, DEEP, LEVEL, INVERT),
  53         /* B4  : H1_PCH_INT_ODL */
  54         PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT),
  55         /* B5  : PCIE_CLKREQ0_N */
  56         PAD_NC(GPP_B5, NONE),
  57         /* B6  : PCIE_CLKREQ1_N */
  58         PAD_NC(GPP_B6, NONE),
  59         /* B7  : PCIE_CLKREQ2_N */
  60         PAD_NC(GPP_B7, NONE),
  61         /* B8  : WLAN_CLKREQ_ODL */
  62         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
  63         /* B9  : PCIE_CLKREQ4_N */
  64         PAD_NC(GPP_B9, NONE),
  65         /* B10 : PCIE_CLKREQ5_N */
  66         PAD_NC(GPP_B10, NONE),
  67         /* B11 : PMCALERT_N */
  68         PAD_NC(GPP_B11, NONE),
  69         /* B12 : AP_SLP_S0_L */
  70         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  71         /* B13 : PLT_RST_L */
  72         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  73         /* B14 : SPKR/GSPI0_CS1_N */
  74         PAD_NC(GPP_B14, NONE),
  75 #if CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50)
  76         /* B15 : H1_SLAVE_SPI_CS_L */
  77         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
  78         /* B16 : H1_SLAVE_SPI_CLK */
  79         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
  80         /* B17 : H1_SLAVE_SPI_MISO_R */
  81         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
  82         /* B18 : H1_SLAVE_SPI_MOSI_R */
  83         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
  84 #else /* BOARD_GOOGLE_BASEBOARD_DEDEDE_TPM2 */
  85         /* Nothing connected on GSPI1 */
  86         PAD_NC(GPP_B15, NONE),
  87         /*
  88          * B16: AP_CBI_EEPROM_WP_L
  89          *
  90          * We default to 0 to keep the EEPROM protected until we know it is safe to
  91          * deassert the write protect signal.
  92          */
  93         PAD_CFG_GPO(GPP_B16, 0, DEEP),
  94         PAD_NC(GPP_B17, NONE),
  95         PAD_NC(GPP_B18, NONE),
  96 #endif
  97         /* B19 : GSPI1_CS0_N */
  98         PAD_NC(GPP_B19, NONE),
  99         /* B20 : GSPI1_CLK */
 100         PAD_NC(GPP_B20, NONE),
 101         /* B21 : GSPI1_MISO */
 102         PAD_NC(GPP_B21, NONE),
 103         /* B22 : GSPI1_MOSI */
 104         PAD_NC(GPP_B22, NONE),
 105         /* B23 : EC_AP_USB_C1_HDMI_HPD */
 106         PAD_CFG_NF(GPP_B23, NONE, DEEP, NF1),
 107
 108         /* C0  : RAM_STRAP_0 */
 109         PAD_CFG_GPI(GPP_C0, NONE, DEEP),
 110         /* C1  : GPP_C1 */
 111         PAD_NC(GPP_C1, NONE),
 112         /* C2  : GPP_C2 */
 113         PAD_NC(GPP_C2, NONE),
 114         /* C3  : RAM_STRAP_1 */
 115         PAD_CFG_GPI(GPP_C3, NONE, DEEP),
 116         /* C4  : RAM_STRAP_2 */
 117         PAD_CFG_GPI(GPP_C4, NONE, DEEP),
 118         /* C5  : RAM_STRAP_3 */
 119         PAD_CFG_GPI(GPP_C5, NONE, DEEP),
 120         /* C6  : PMC_SUSWARN_N */
 121         PAD_NC(GPP_C6, NONE),
 122         /* C7  : PMC_SUSACK_N */
 123         PAD_NC(GPP_C7, NONE),
 124         /* C8  : GPP_C8/UART0_RXD */
 125         PAD_NC(GPP_C8, NONE),
 126         /* C9  : GPP_C9/UART0_TXD */
 127         PAD_NC(GPP_C9, NONE),
 128         /* C10 : GPP_C10/UART0_RTSB */
 129         PAD_NC(GPP_C10, NONE),
 130         /* C11 : AP_WP_OD */
 131         PAD_CFG_GPI(GPP_C11, NONE, DEEP),
 132         /* C12 : AP_PEN_DET_ODL */
 133         PAD_NC(GPP_C12, NONE),
 134         /* C13 : GPP_C13/UART1_TXD */
 135         PAD_NC(GPP_C13, NONE),
 136         /* C14 : EC_IN_RW_OD */
 137         PAD_CFG_GPI(GPP_C14, NONE, DEEP),
 138         /* C15 : EC_AP_MKBP_INT_L */
 139         PAD_CFG_GPI_APIC(GPP_C15, UP_20K, PLTRST, LEVEL, INVERT),
 140         /* C16 : AP_I2C_TRACKPAD_SDA_3V3 */
 141         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 142         /* C17 : AP_I2C_TRACKPAD_SCL_3V3 */
 143         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 144         /* C18 : AP_I2C_EMR_SDA */
 145         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 146         /* C19 : AP_I2C_EMR_SCL */
 147         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 148         /* C20 : UART_DBG_TX_AP_RX */
 149         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 150         /* C21 : UART_AP_TX_DBG_RX */
 151         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 152         /* C22 : UART2_RTS_N */
 153         PAD_NC(GPP_C22, DN_20K),
 154         /* C23 : UART2_CTS_N */
 155         PAD_NC(GPP_C23, DN_20K),
 156
 157         /* D0  : WWAN_HOST_WAKE */
 158         PAD_NC(GPP_D0, NONE),
 159         /* D1  : WLAN_PERST_L */
 160         PAD_CFG_GPO(GPP_D1, 1, DEEP),
 161         /* D2  : WLAN_INT_L */
 162         PAD_NC(GPP_D2, NONE),
 163         /* D3  : WLAN_PCIE_WAKE_ODL */
 164         PAD_CFG_GPI_SCI_LOW(GPP_D3, NONE, DEEP, EDGE_SINGLE),
 165         /* D4  : TOUCH_INT_ODL */
 166         PAD_CFG_GPI_APIC(GPP_D4, NONE, PLTRST, LEVEL, INVERT),
 167         /* D5  : TOUCH_RESET_L */
 168         PAD_CFG_GPO(GPP_D5, 1, DEEP),
 169         /* D6  : EN_PP3300_TOUCH_S0 */
 170         PAD_CFG_GPO(GPP_D6, 1, DEEP),
 171         /* D7  : EMR_INT_ODL */
 172         PAD_NC(GPP_D7, NONE),
 173         /* D8  : GPP_D8/GSPI2_CS0B/UART0A_RXD */
 174         PAD_NC(GPP_D8, NONE),
 175         /* D9  : GPP_D9/GSPI2_CLK/UART0A_TXD */
 176         PAD_NC(GPP_D9, NONE),
 177         /* D10 : GPP_D10/GSPI2_MISO/UART0A_RTSB */
 178         PAD_NC(GPP_D10, NONE),
 179         /* D11 : GPP_D11/GSPI2_MOSI/UART0A_CTSB */
 180         PAD_NC(GPP_D11, NONE),
 181         /* D12 : WCAM_RST_L */
 182         PAD_CFG_GPO(GPP_D12, 0, PLTRST),
 183         /* D13 : EN_PP2800_CAMERA */
 184         PAD_CFG_GPO(GPP_D13, 0, PLTRST),
 185         /* D14 : EN_PP1200_CAMERA */
 186         PAD_CFG_GPO(GPP_D14, 0, PLTRST),
 187         /* D15 : UCAM_RST_L */
 188         PAD_CFG_GPO(GPP_D15, 0, PLTRST),
 189         /* D16 : HP_INT_ODL */
 190         PAD_CFG_GPI_INT(GPP_D16, NONE, PLTRST, EDGE_BOTH),
 191         /* D17 : EN_SPK */
 192         PAD_CFG_GPO(GPP_D17, 0, PLTRST),
 193         /* D18 : I2S_MCLK */
 194         PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
 195         /* D19 : WWAN_WLAN_COEX1 */
 196         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 197         /* D20 : WWAN_WLAN_COEX2 */
 198         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 199         /* D21 : WWAN_WLAN_COEX3 */
 200         PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1),
 201         /* D22 : AP_I2C_SUB_SDA*/
 202         PAD_NC(GPP_D22, NONE),
 203         /* D23 : AP_I2C_SUB_SCL */
 204         PAD_NC(GPP_D23, NONE),
 205
 206         /* E0  : CLK_24M_UCAM */
 207         PAD_CFG_NF(GPP_E0, NONE, DEEP, NF2),
 208         /* E1  : EMR_RESET_L */
 209         PAD_NC(GPP_E1, NONE),
 210         /* E2  : CLK_24M_WCAM */
 211         PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
 212         /* E3  : GPP_E3/SATA_0_DEVSLP */
 213         PAD_NC(GPP_E3, NONE),
 214         /* E4  : IMGCLKOUT_2 */
 215         PAD_NC(GPP_E4, NONE),
 216         /* E5  : AP_SUB_IO_2 */
 217         PAD_NC(GPP_E5, NONE),
 218         /* E6  : GPP_E6/IMGCLKOUT_3 */
 219         PAD_NC(GPP_E6, NONE),
 220         /* E7  : GPP_E7/SATA_1_DEVSLP */
 221         PAD_NC(GPP_E7, NONE),
 222         /* E8  : GPP_E8/SATA_0_GP */
 223         PAD_NC(GPP_E8, NONE),
 224         /* E9  : GPP_E9/SML_CLK0/SATA_1_GP */
 225         PAD_NC(GPP_E9, NONE),
 226         /* E10 : GPP_E10/SML_DATA0 */
 227         PAD_NC(GPP_E10, NONE),
 228         /* E11 : AP_I2C_SUB_INT_ODL */
 229         PAD_NC(GPP_E11, NONE),
 230         /* E12 : GPP_E12/IMGCLKOUT_4 */
 231         PAD_NC(GPP_E12, NONE),
 232         /* E13 : GPP_E13/DDI0_DDC_SCL */
 233         PAD_NC(GPP_E13, NONE),
 234         /* E14 : GPP_E14/DDI0_DDC_SDA */
 235         PAD_NC(GPP_E14, NONE),
 236         /* E15 : GPP_E15/DDI1_DDC_SCL */
 237         PAD_NC(GPP_E15, NONE),
 238         /* E16 : GPP_E16/DDI1_DDC_SDA */
 239         PAD_NC(GPP_E16, NONE),
 240         /* E17 : HDMI_DDC_SCL */
 241         PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 242         /* E18 : HDMI_DDC_SDA */
 243         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
 244         /* E19 : GPP_E19/IMGCLKOUT_5/PCIE_LNK_DOWN */
 245         PAD_NC(GPP_E19, NONE),
 246         /* E20 : CNV_BRI_DT_R */
 247         PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
 248         /* E21 : CNV_BRI_RSP */
 249         PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
 250         /* E22 : CNV_RGI_DT_R */
 251         PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1),
 252         /* E23 : CNV_RGI_RSP */
 253         PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1),
 254
 255         /* F4  : CNV_RF_RST_L */
 256         PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 257         /* F7  : EMMC_CMD */
 258         PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
 259         /* F8  : EMMC_DATA0 */
 260         PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
 261         /* F9  : EMMC_DATA1 */
 262         PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
 263         /* F10 : EMMC_DATA2 */
 264         PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1),
 265         /* F11 : EMMC_DATA3 */
 266         PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
 267         /* F12 : EMMC_DATA4 */
 268         PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
 269         /* F13 : EMMC_DATA5 */
 270         PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
 271         /* F14 : EMMC_DATA6 */
 272         PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
 273         /* F15 : EMMC_DATA7 */
 274         PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
 275         /* F16 : EMMC_RCLK */
 276         PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
 277         /* F17 : EMMC_CLK */
 278         PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
 279         /* F18 : EMMC_RESET_N */
 280         PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
 281
 282         /* G0  : SD_CMD */
 283         PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1),
 284         /* G1  : SD_DATA0 */
 285         PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1),
 286         /* G2  : SD_DATA1 */
 287         PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1),
 288         /* G3  : SD_DATA2 */
 289         PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1),
 290         /* G4  : SD_DATA3 */
 291         PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1),
 292         /* G5  : SD_CD_ODL */
 293         PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
 294         /* G6  : SD_CLK */
 295         PAD_CFG_NF(GPP_G6, NATIVE, DEEP, NF1),
 296         /* G7  : SD_SDIO_WP */
 297         PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
 298
 299         /* H0  : WWAN_PERST */
 300         PAD_NC(GPP_H0, NONE),
 301         /* H1  : EN_PP3300_SD_U */
 302         PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1),
 303         /* H2  : CNV_CLKREQ0 */
 304         PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
 305         /* H3  : GPP_H03/SX_EXIT_HOLDOFF_N */
 306         PAD_NC(GPP_H3, NONE),
 307         /* H4  : AP_I2C_TS_SDA */
 308         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 309         /* H5  : AP_I2C_TS_SCL */
 310         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 311         /* H6  : AP_I2C_CAM_SDA */
 312         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 313         /* H7  : AP_I2C_CAM_SCL */
 314         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 315         /* H8  : AP_I2C_AUDIO_SDA */
 316         PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
 317         /* H9  : AP_I2C_AUDIO_SCL */
 318         PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
 319         /* H10 : CPU_C10_GATE_L */
 320         PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1),
 321         /* H11 : GPP_H11/AV_I2S2_SCLK */
 322         PAD_NC(GPP_H11, NONE),
 323         /* H12 : GPP_H12/AVS_I2S2_SFRM/CNF_RF_RESET_N */
 324         PAD_NC(GPP_H12, NONE),
 325         /* H13 : GPP_H13/AVS_I2S2_TXD/MODEM_CLKREQ */
 326         PAD_NC(GPP_H13, NONE),
 327         /* H14 : GPP_H14/AVS_I2S2_RXD */
 328         PAD_NC(GPP_H14, NONE),
 329         /* H15 : I2S_SPK_BCLK */
 330         PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1),
 331         /* H16 : AP_SUB_IO_L */
 332         PAD_NC(GPP_H16, NONE),
 333         /* H17 : WWAN_RST_L */
 334         PAD_NC(GPP_H17, NONE),
 335         /* H18 : WLAN_DISABLE_L */
 336         PAD_CFG_GPO(GPP_H18, 1, DEEP),
 337         /* H19 : BT_DISABLE_L */
 338         PAD_CFG_GPO(GPP_H19, 1, DEEP),
 339
 340         /* R0  : I2S_HP_BCLK */
 341         PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2),
 342         /* R1  : I2S_HP_LRCK */
 343         PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2),
 344         /* R2  : I2S_HP_AUDIO */
 345         PAD_CFG_NF(GPP_R2, NONE, DEEP, NF2),
 346         /* R3  : I2S_HP_MIC */
 347         PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2),
 348         /* R4  : GPP_R04/HDA_RST_N */
 349         PAD_NC(GPP_R4, NONE),
 350         /* R5  : GPP_R05/HDA_SDI1/AVS_I2S1_RXD */
 351         PAD_NC(GPP_R5, NONE),
 352         /* R6  : I2S_SPK_LRCK */
 353         PAD_CFG_NF(GPP_R6, NONE, DEEP, NF1),
 354         /* R7  :  I2S_SPK_AUDIO */
 355         PAD_CFG_NF(GPP_R7, NONE, DEEP, NF1),
 356
 357         /* S0  : RAM_STRAP_4 */
 358         PAD_CFG_GPI(GPP_S0, NONE, DEEP),
 359         /* S1  : RSVD_STRAP */
 360         PAD_NC(GPP_S1, NONE),
 361         /* S2  : DMIC1_CLK */
 362         PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2),
 363         /* S3  : DMIC1_DATA */
 364         PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2),
 365         /* S4  : GPP_S04/SNDW1_CLK */
 366         PAD_NC(GPP_S4, NONE),
 367         /* S5  : GPP_S05/SNDW1_DATA */
 368         PAD_NC(GPP_S5, NONE),
 369         /* S6  :  DMIC0_CLK */
 370         PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2),
 371         /* S7  : DMIC0_DATA */
 372         PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2),
 373
 374         /* GPD0 : AP_BATLOW_L */
 375         PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
 376         /* GPD1 : GPP_GPD1/ACPRESENT */
 377         PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
 378         /* GPD2 : EC_AP_WAKE_ODL */
 379         PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 380         /* GPD3 : EC_AP_PWR_BTN_ODL */
 381         PAD_CFG_NF(GPD3, UP_20K, DEEP, NF1),
 382         /* GPD4 : AP_SLP_S3_L */
 383         PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
 384         /* GPD5 : AP_SLP_S4_L */
 385         PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
 386         /* GPD6 : AP_SLP_A_L */
 387         PAD_NC(GPD6, NONE),
 388         /* GPD7 : GPP_GPD7 */
 389         PAD_NC(GPD7, NONE),
 390         /* GPD8 : WLAN_SUSCLK */
 391         PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
 392         /* GPD9 : AP_SLP_WLAN_L */
 393         PAD_NC(GPD9, NONE),
 394         /* GPD10 : AP_SLP_S5_L */
 395         PAD_NC(GPD10, NONE),
 396
 397         /* SD card detect virtual GPIO */
 398         PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, PLTRST),
 399
 400 };
 401
 402 /* Early pad configuration in bootblock */
 403 static const struct pad_config early_gpio_table[] = {
 404         /* B4 : H1_PCH_INT_ODL */
 405         PAD_CFG_GPI_APIC(GPP_B4, NONE, PLTRST, LEVEL, INVERT),
 406 #if CONFIG(BOARD_GOOGLE_BASEBOARD_DEDEDE_CR50)
 407         /* B15 : H1_SLAVE_SPI_CS_L */
 408         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 409         /* B16 : H1_SLAVE_SPI_CLK */
 410         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
 411         /* B17 : H1_SLAVE_SPI_MISO_R */
 412         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 413         /* B18 : H1_SLAVE_SPI_MOSI_R */
 414         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 415 #endif
 416
 417         /* C0  : RAM_STRAP_0 */
 418         PAD_CFG_GPI(GPP_C0, NONE, DEEP),
 419         /* C3  : RAM_STRAP_1 */
 420         PAD_CFG_GPI(GPP_C3, NONE, DEEP),
 421         /* C4  : RAM_STRAP_2 */
 422         PAD_CFG_GPI(GPP_C4, NONE, DEEP),
 423         /* C5  : RAM_STRAP_3 */
 424         PAD_CFG_GPI(GPP_C5, NONE, DEEP),
 425
 426         /* C14 : EC_IN_RW_OD */
 427         PAD_CFG_GPI(GPP_C14, NONE, DEEP),
 428
 429         /* C20 : UART2 RX */
 430         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1),
 431         /* C21 : UART2 TX */
 432         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
 433
 434         /* D1  : WLAN_PERST_L */
 435         PAD_CFG_GPO(GPP_D1, 1, DEEP),
 436
 437         /* H19 : BT_DISABLE_L */
 438         PAD_CFG_GPO(GPP_H19, 0, DEEP),
 439
 440         /* S0  : RAM_STRAP_4 */
 441         PAD_CFG_GPI(GPP_S0, NONE, DEEP),
 442 };
 443
 444 const struct pad_config *baseboard_gpio_table(size_t *num)
 445 {
 446         *num = ARRAY_SIZE(gpio_table);
 447         return gpio_table;
 448 }
 449
 450 const struct pad_config *__weak variant_override_gpio_table(size_t *num)
 451 {
 452         *num = 0;
 453         return NULL;
 454 }
 455
 456 const struct pad_config *__weak variant_early_gpio_table(size_t *num)
 457 {
 458         *num = ARRAY_SIZE(early_gpio_table);
 459         return early_gpio_table;
 460 }
 461
 462 /* GPIO settings before entering sleep. */
 463 static const struct pad_config sleep_gpio_table[] = {
 464 };
 465
 466 const struct pad_config *__weak variant_sleep_gpio_table(size_t *num)
 467 {
 468         *num = ARRAY_SIZE(sleep_gpio_table);
 469         return sleep_gpio_table;
 470 }
 471
 472 static const struct pad_config romstage_gpio_table[] = {
 473         /* Enable touchscreen, hold in reset */
 474         /* D5  : TOUCH_RESET_L */
 475         PAD_CFG_GPO(GPP_D5, 0, DEEP),
 476         /* D6  : EN_PP3300_TOUCH_S0 */
 477         PAD_CFG_GPO(GPP_D6, 1, DEEP),
 478 };
 479
 480 const struct pad_config *__weak variant_romstage_gpio_table(size_t *num)
 481 {
 482         *num = ARRAY_SIZE(romstage_gpio_table);
 483         return romstage_gpio_table;
 484 }
 485
 486 static const struct cros_gpio cros_gpios[] = {
 487         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_COMM0_NAME),
 488         CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_COMM0_NAME),
 489 };
 490
 491 DECLARE_WEAK_CROS_GPIOS(cros_gpios);
 492
 493 const gpio_t *__weak variant_hpd_gpios(size_t *num)
 494 {
 495         *num = 0;
 496         return NULL;
 497 }