mainboard/intel/avenuecity_crb: Update full IIO configuration
[coreboot2.git] / src / mainboard / google / foster / pmic.c
blob5ea04856bf8dce004729098fea5826b09b51c437
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <console/console.h>
4 #include <delay.h>
5 #include <device/i2c_simple.h>
6 #include <reset.h>
7 #include <stdint.h>
9 #include "pmic.h"
11 enum {
12 MAX77620_I2C_ADDR = 0x3c
15 struct max77620_init_reg {
16 u8 reg;
17 u8 val;
18 u8 delay;
21 static void pmic_write_reg(unsigned int bus, uint8_t reg, uint8_t val, int delay)
23 if (i2c_writeb(bus, MAX77620_I2C_ADDR, reg, val)) {
24 printk(BIOS_ERR, "%s: reg = 0x%02X, value = 0x%02X failed!\n",
25 __func__, reg, val);
26 /* Reset the board on any PMIC write error */
27 board_reset();
28 } else {
29 if (delay)
30 udelay(500);
34 void pmic_init(unsigned int bus)
36 /* Setup/Enable GPIO5 - VDD_CPU_REG_EN */
37 pmic_write_reg(bus, MAX77620_GPIO5_REG, 0x09, 1);
39 /* Setup/Enable GPIO1 - VDD_HDMI_5V0_BST_EN -- ??? */
40 pmic_write_reg(bus, MAX77620_GPIO1_REG, 0x09, 1);
42 /* GPIO 0,1,5,6,7 = GPIO, 2,3,4 = alt mode */
43 pmic_write_reg(bus, MAX77620_AME_GPIO, 0x1c, 1);
45 /* Disable SD1 Remote Sense, Set SD1 for LPDDR4 to 1.125v? */
46 pmic_write_reg(bus, MAX77620_CNFG2SD_REG, 0x04, 1);
48 pmic_write_reg(bus, MAX77620_SD1_REG, 0x2a, 1);
50 /* CNFG1_L2 = 0xF2 for 3.3v, enabled */
51 pmic_write_reg(bus, MAX77620_CNFG1_L2_REG, 0xf2, 1);
53 /* CNFG1_L1 = 0xCA for 1.05v, enabled */
54 pmic_write_reg(bus, MAX77620_CNFG1_L1_REG, 0xca, 1);
56 printk(BIOS_DEBUG, "PMIC init done\n");