src/mainboard/google/nyan/devicetree.cb

   1 ## SPDX-License-Identifier: GPL-2.0-only
   2
   3 chip soc/nvidia/tegra124
   4         device cpu_cluster 0 on end
   5 # N.B. We are not using the device tree in an effective way.
   6 # We need to change this in future such that the on-SoC
   7 # devices are 'chips', which will allow us to go at them
   8 # in parallel. This is even easier on the ARM SoCs since there
   9 # are no single-access resources such as the infamous
  10 # 0xcf8/0xcfc registers found on PCs.
  11         register "display_controller" = "TEGRA_ARM_DISPLAYA"
  12         register "xres" = "1366"
  13         register "yres" = "768"
  14
  15         # bits per pixel and color depth
  16         register "framebuffer_bits_per_pixel" = "16"
  17         register "color_depth" = "6"
  18         # "6" is defined as COLOR_DEPTH_B5G6R5 in dc_reg.h
  19
  20         register "panel_bits_per_pixel" = "18"
  21
  22         # With some help from the mainbaord designer
  23         register "backlight_en_gpio" = "GPIO(H2)"
  24         register "lvds_shutdown_gpio" = "0"
  25         register "backlight_vdd_gpio" = "GPIO(P2)"
  26         register "panel_vdd_gpio" = "0"
  27         register "pwm" = "1"
  28
  29         # Various panel delay times
  30         register "vdd_delay_ms" = "200"
  31         register "pwm_to_bl_delay_ms" = "10"
  32         register "vdd_to_hpd_delay_ms" = "200"
  33         register "hpd_unplug_min_us" = "2000"
  34         register "hpd_plug_min_us" = "250"
  35         register "hpd_irq_min_us" = "250"
  36
  37 # How to compute these: xrandr --verbose will give you this:
  38 #Detailed mode: Clock 285.250 MHz, 272 mm x 181 mm
  39 #               2560 2608 2640 2720 hborder 0
  40 #               1700 1703 1713 1749 vborder 0
  41 #Then you can compute your values:
  42 #H front porch = 2608 - 2560 = 48
  43 #H sync = 2640 - 2608 = 32
  44 #H back porch = 2720 - 2640 = 80
  45 #V front porch = 1703 - 1700 = 3
  46 #V sync = 1713 - 1703 = 10
  47 #V back porch = 1749 - 1713 = 36
  48 #href_to_sync and vref_to_sync are from the vendor
  49 #this is just an example for a Pixel panel; other panels differ.
  50 # Here is a peppy panel:
  51 #  1366x768 (0x45)   76.4MHz -HSync -VSync *current +preferred
  52 #        h: width  1366 start 1502 end 1532 total 1592
  53 #        v: height  768 start  776 end  788 total  800
  54         register "href_to_sync" = "1"
  55         register "hfront_porch" = "136"
  56         register "hsync_width" = "30"
  57         register "hback_porch" = "60"
  58
  59         register "vref_to_sync" = "1"
  60         register "vfront_porch" = "8"
  61         register "vsync_width" = "12"
  62         register "vback_porch" = "12"
  63
  64         register "pixel_clock" = "76400000"
  65
  66         # link configurations
  67         register "lane_count" = "1"
  68         register "enhanced_framing" = "1"
  69         register "link_bw" = "10"
  70         # "10" is defined as SOR_LINK_SPEED_G2_7 in sor.h
  71
  72         register "drive_current" = "0x40404040"
  73         register "preemphasis" = "0x0f0f0f0f"
  74         register "postcursor" = "0"
  75 end