src/mainboard/google/nyan_big/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <device/mmio.h>
   4 #include <boot/coreboot_tables.h>
   5 #include <device/device.h>
   6 #include <gpio.h>
   7 #include <soc/addressmap.h>
   8 #include <soc/clk_rst.h>
   9 #include <soc/clock.h>
  10 #include <soc/mc.h>
  11 #include <soc/nvidia/tegra/i2c.h>
  12 #include <soc/pmc.h>
  13 #include <soc/spi.h>
  14 #include <soc/nvidia/tegra/usb.h>
  15 #include <symbols.h>
  16
  17 static struct clk_rst_ctlr *clk_rst = (void *)TEGRA_CLK_RST_BASE;
  18
  19 static void set_clock_sources(void)
  20 {
  21         /*
  22          * The max98090 codec and the temperature sensor are on I2C1. These
  23          * can both run at 400 KHz, but the kernel sets the bus to 100 KHz.
  24          */
  25         clock_configure_i2c_scl_freq(i2c1, PLLP, 100);
  26
  27         /*
  28          * MMC3 and MMC4: Set base clock frequency for SD Clock to Tegra MMC's
  29          * maximum speed (48MHz) so we can change SDCLK by second stage divisor
  30          * in payloads, without touching base clock.
  31          */
  32         clock_configure_source(sdmmc3, PLLP, 48000);
  33         clock_configure_source(sdmmc4, PLLP, 48000);
  34
  35         /* External peripheral 1: audio codec (max98090) using 12MHz CLK1.
  36          * Note the source id of CLK_M for EXTPERIPH1 is 3. */
  37         clock_configure_irregular_source(extperiph1, CLK_M, 12000, 3);
  38
  39         /*
  40          * We need 1.5MHz. So, we use CLK_M. CLK_DIVIDER macro returns a divisor
  41          * (0xe) a little bit off from the ideal value (0xd) but it's good
  42          * enough for beeps. The source id of CLK_M for I2S is 6.
  43          */
  44         clock_configure_irregular_source(i2s1, CLK_M, 1500, 6);
  45
  46         /* Note source id of PLLP for HOST1x is 4. */
  47         clock_configure_irregular_source(host1x, PLLP, 408000, 4);
  48
  49         /* Use PLLD_OUT0 as clock source for disp1 */
  50         clrsetbits32(&clk_rst->clk_src_disp1,
  51                      CLK_SOURCE_MASK | CLK_DIVISOR_MASK,
  52                      2 /*PLLD_OUT0 */ << CLK_SOURCE_SHIFT);
  53 }
  54
  55 static void setup_pinmux(void)
  56 {
  57         // I2C1 clock.
  58         pinmux_set_config(PINMUX_GEN1_I2C_SCL_INDEX,
  59                           PINMUX_GEN1_I2C_SCL_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
  60         // I2C1 data.
  61         pinmux_set_config(PINMUX_GEN1_I2C_SDA_INDEX,
  62                           PINMUX_GEN1_I2C_SDA_FUNC_I2C1 | PINMUX_INPUT_ENABLE);
  63         // I2C2 clock.
  64         pinmux_set_config(PINMUX_GEN2_I2C_SCL_INDEX,
  65                           PINMUX_GEN2_I2C_SCL_FUNC_I2C2 | PINMUX_INPUT_ENABLE |
  66                           PINMUX_OPEN_DRAIN);
  67         // I2C2 data.
  68         pinmux_set_config(PINMUX_GEN2_I2C_SDA_INDEX,
  69                           PINMUX_GEN2_I2C_SDA_FUNC_I2C2 | PINMUX_INPUT_ENABLE |
  70                           PINMUX_OPEN_DRAIN);
  71         // I2C4 (DDC) clock.
  72         pinmux_set_config(PINMUX_DDC_SCL_INDEX,
  73                           PINMUX_DDC_SCL_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
  74         // I2C4 (DDC) data.
  75         pinmux_set_config(PINMUX_DDC_SDA_INDEX,
  76                           PINMUX_DDC_SDA_FUNC_I2C4 | PINMUX_INPUT_ENABLE);
  77
  78         // TODO(hungte) Revice pinmux setup, make nice little SoC functions for
  79         // every single logical thing instead of dumping a wall of code below.
  80         uint32_t pin_up = PINMUX_PULL_UP | PINMUX_INPUT_ENABLE,
  81                  pin_down = PINMUX_PULL_DOWN | PINMUX_INPUT_ENABLE,
  82                  pin_none = PINMUX_PULL_NONE | PINMUX_INPUT_ENABLE;
  83
  84         // MMC3 (sdcard reader)
  85         pinmux_set_config(PINMUX_SDMMC3_CLK_INDEX,
  86                           PINMUX_SDMMC3_CLK_FUNC_SDMMC3 | pin_none);
  87         pinmux_set_config(PINMUX_SDMMC3_CMD_INDEX,
  88                           PINMUX_SDMMC3_CMD_FUNC_SDMMC3 | pin_up);
  89         pinmux_set_config(PINMUX_SDMMC3_DAT0_INDEX,
  90                           PINMUX_SDMMC3_DAT0_FUNC_SDMMC3 | pin_up);
  91         pinmux_set_config(PINMUX_SDMMC3_DAT1_INDEX,
  92                           PINMUX_SDMMC3_DAT1_FUNC_SDMMC3 | pin_up);
  93         pinmux_set_config(PINMUX_SDMMC3_DAT2_INDEX,
  94                           PINMUX_SDMMC3_DAT2_FUNC_SDMMC3 | pin_up);
  95         pinmux_set_config(PINMUX_SDMMC3_DAT3_INDEX,
  96                           PINMUX_SDMMC3_DAT3_FUNC_SDMMC3 | pin_up);
  97         pinmux_set_config(PINMUX_SDMMC3_CLK_LB_IN_INDEX,
  98                           PINMUX_SDMMC3_CLK_LB_IN_FUNC_SDMMC3 | pin_up);
  99         pinmux_set_config(PINMUX_SDMMC3_CLK_LB_OUT_INDEX,
 100                           PINMUX_SDMMC3_CLK_LB_OUT_FUNC_SDMMC3 | pin_down);
 101
 102         // MMC3 Card Detect pin.
 103         gpio_input_pullup(GPIO(V2));
 104         // Disable SD card reader power so it can be reset even on warm boot.
 105         // Payloads must enable power before accessing SD card slots.
 106         gpio_output(GPIO(R0), 0);
 107
 108         // MMC4 (eMMC)
 109         pinmux_set_config(PINMUX_SDMMC4_CLK_INDEX,
 110                           PINMUX_SDMMC4_CLK_FUNC_SDMMC4 | pin_none);
 111         pinmux_set_config(PINMUX_SDMMC4_CMD_INDEX,
 112                           PINMUX_SDMMC4_CMD_FUNC_SDMMC4 | pin_up);
 113         pinmux_set_config(PINMUX_SDMMC4_DAT0_INDEX,
 114                           PINMUX_SDMMC4_DAT0_FUNC_SDMMC4 | pin_up);
 115         pinmux_set_config(PINMUX_SDMMC4_DAT1_INDEX,
 116                           PINMUX_SDMMC4_DAT1_FUNC_SDMMC4 | pin_up);
 117         pinmux_set_config(PINMUX_SDMMC4_DAT2_INDEX,
 118                           PINMUX_SDMMC4_DAT2_FUNC_SDMMC4 | pin_up);
 119         pinmux_set_config(PINMUX_SDMMC4_DAT3_INDEX,
 120                           PINMUX_SDMMC4_DAT3_FUNC_SDMMC4 | pin_up);
 121         pinmux_set_config(PINMUX_SDMMC4_DAT4_INDEX,
 122                           PINMUX_SDMMC4_DAT4_FUNC_SDMMC4 | pin_up);
 123         pinmux_set_config(PINMUX_SDMMC4_DAT5_INDEX,
 124                           PINMUX_SDMMC4_DAT5_FUNC_SDMMC4 | pin_up);
 125         pinmux_set_config(PINMUX_SDMMC4_DAT6_INDEX,
 126                           PINMUX_SDMMC4_DAT6_FUNC_SDMMC4 | pin_up);
 127         pinmux_set_config(PINMUX_SDMMC4_DAT7_INDEX,
 128                           PINMUX_SDMMC4_DAT7_FUNC_SDMMC4 | pin_up);
 129
 130         /* We pull the USB VBUS signals up but keep them as inputs since the
 131          * voltage source likes to drive them low on overcurrent conditions */
 132         gpio_input_pullup(GPIO(N4));    /* USB VBUS EN0 */
 133         gpio_input_pullup(GPIO(N5));    /* USB VBUS EN1 */
 134
 135         /* Clock output 1 (for external peripheral) */
 136         pinmux_set_config(PINMUX_DAP_MCLK1_INDEX,
 137                           PINMUX_DAP_MCLK1_FUNC_EXTPERIPH1 | PINMUX_PULL_NONE);
 138
 139         /* I2S1 */
 140         pinmux_set_config(PINMUX_DAP2_DIN_INDEX,
 141                           PINMUX_DAP2_DIN_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
 142         pinmux_set_config(PINMUX_DAP2_DOUT_INDEX,
 143                           PINMUX_DAP2_DOUT_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
 144         pinmux_set_config(PINMUX_DAP2_FS_INDEX,
 145                           PINMUX_DAP2_FS_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
 146         pinmux_set_config(PINMUX_DAP2_SCLK_INDEX,
 147                           PINMUX_DAP2_SCLK_FUNC_I2S1 | PINMUX_INPUT_ENABLE);
 148
 149         /* PWM1 */
 150         pinmux_set_config(PINMUX_GPIO_PH1_INDEX,
 151                           PINMUX_GPIO_PH1_FUNC_PWM1 | PINMUX_PULL_NONE);
 152
 153          /* DP HPD */
 154         pinmux_set_config(PINMUX_DP_HPD_INDEX,
 155                         PINMUX_DP_HPD_FUNC_DP | PINMUX_INPUT_ENABLE);
 156 }
 157
 158 static void setup_kernel_info(void)
 159 {
 160         // Setup required information for Linux kernel.
 161
 162         // pmc.odmdata: [18:19]: console type, [15:17]: UART id.
 163         // TODO(hungte) This should be done by filling BCT values, or derived
 164         // from CONFIG_CONSOLE_SERIAL_UART[A-E]. Right now we simply copy the
 165         // value defined in BCT.
 166         struct tegra_pmc_regs *pmc = (void*)TEGRA_PMC_BASE;
 167         write32(&pmc->odmdata, 0x80080000);
 168
 169         // Not strictly info, but kernel graphics driver needs this region locked down
 170         struct tegra_mc_regs *mc = (void *)TEGRA_MC_BASE;
 171         write32(&mc->video_protect_bom, 0);
 172         write32(&mc->video_protect_size_mb, 0);
 173         write32(&mc->video_protect_reg_ctrl, 1);
 174 }
 175
 176 static void setup_ec_spi(void)
 177 {
 178         tegra_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS);
 179 }
 180
 181 static void mainboard_init(struct device *dev)
 182 {
 183         set_clock_sources();
 184
 185         clock_external_output(1); /* For external MAX98090 audio codec. */
 186
 187         /*
 188          * Confirmed by NVIDIA hardware team, we need to take ALL audio devices
 189          * conntected to AHUB (AUDIO, APBIF, I2S, DAM, AMX, ADX, SPDIF, AFC) out
 190          * of reset and clock-enabled, otherwise reading AHUB devices (In our
 191          * case, I2S/APBIF/AUDIO<XBAR>) will hang.
 192          */
 193         clock_enable_clear_reset(CLK_L_GPIO | CLK_L_I2C1 | CLK_L_SDMMC4 |
 194                                  CLK_L_I2S0 | CLK_L_I2S1 | CLK_L_I2S2 |
 195                                  CLK_L_SPDIF | CLK_L_USBD | CLK_L_DISP1 |
 196                                  CLK_L_HOST1X | CLK_L_PWM,
 197
 198                                  CLK_H_EMC | CLK_H_I2C2 | CLK_H_PMC |
 199                                  CLK_H_MEM | CLK_H_USB3,
 200
 201                                  CLK_U_CSITE | CLK_U_SDMMC3,
 202
 203                                  CLK_V_I2C4 | CLK_V_EXTPERIPH1 | CLK_V_APBIF |
 204                                  CLK_V_AUDIO | CLK_V_I2S3 | CLK_V_I2S4 |
 205                                  CLK_V_DAM0 | CLK_V_DAM1 | CLK_V_DAM2,
 206
 207                                  CLK_W_DVFS | CLK_W_AMX0 | CLK_W_ADX0,
 208
 209                                  CLK_X_DPAUX | CLK_X_SOR0 | CLK_X_AMX1 |
 210                                  CLK_X_ADX1 | CLK_X_AFC0 | CLK_X_AFC1 |
 211                                  CLK_X_AFC2 | CLK_X_AFC3 | CLK_X_AFC4 |
 212                                  CLK_X_AFC5);
 213
 214         usb_setup_utmip((void*)TEGRA_USBD_BASE);
 215         /* USB2 is the camera, we don't need it in firmware */
 216         usb_setup_utmip((void*)TEGRA_USB3_BASE);
 217
 218         setup_pinmux();
 219
 220         i2c_init(0);
 221         i2c_init(1);
 222         i2c_init(3);
 223
 224         setup_kernel_info();
 225         clock_init_arm_generic_timer();
 226         setup_ec_spi();
 227 }
 228
 229 static void mainboard_enable(struct device *dev)
 230 {
 231         dev->ops->init = &mainboard_init;
 232 }
 233
 234 struct chip_operations mainboard_ops = {
 235         .enable_dev = mainboard_enable,
 236 };
 237
 238 void lb_board(struct lb_header *header)
 239 {
 240         struct lb_range *dma;
 241
 242         dma = (struct lb_range *)lb_new_record(header);
 243         dma->tag = LB_TAG_DMA;
 244         dma->size = sizeof(*dma);
 245         dma->range_start = (uintptr_t)_dma_coherent;
 246         dma->range_size = REGION_SIZE(dma_coherent);
 247 }