src/mainboard/google/octopus/variants/baseboard/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <baseboard/gpio.h>
   5 #include <baseboard/variants.h>
   6 #include <types.h>
   7 #include <vendorcode/google/chromeos/chromeos.h>
   8
   9 /*
  10  * Pad configuration in ramstage. The order largely follows the 'GPIO Muxing'
  11  * table found in EDS vol 1, but some pins aren't grouped functionally in
  12  * the table so those were moved for more logical grouping.
  13  */
  14 static const struct pad_config gpio_table[] = {
  15         /* NORTHWEST COMMUNITY GPIOS */
  16         PAD_NC(GPIO_0, DN_20K), /* TCK -- debug header NC */
  17         PAD_NC(GPIO_1, DN_20K), /* TRST_B -- debug header NC */
  18         PAD_NC(GPIO_2, UP_20K), /* TMS -- debug header NC */
  19         PAD_NC(GPIO_3, UP_20K), /* TDI -- debug header NC */
  20         PAD_NC(GPIO_4, UP_20K), /* TDO -- debug header NC */
  21         PAD_NC(GPIO_5, UP_20K), /* JTAGX -- unused */
  22         PAD_NC(GPIO_6, UP_20K), /* CX_PREQ_B -- debug header NC */
  23         PAD_NC(GPIO_7, UP_20K), /* CX_PRDY_B -- debug header NC */
  24         PAD_NC(GPIO_8, DN_20K), /* TRACE_0_CLK_VNN -- debug header NC */
  25         PAD_NC(GPIO_9, DN_20K), /* TRACE_0_DATA0_VNN -- debug header NC */
  26         PAD_NC(GPIO_10, DN_20K), /* TRACE_0_DATA1_VNN -- debug header NC */
  27         PAD_NC(GPIO_11, DN_20K), /* TRACE_0_DATA2_VNN -- debug header NC */
  28         PAD_NC(GPIO_12, DN_20K), /* TRACE_0_DATA3_VNN -- debug header NC */
  29         PAD_NC(GPIO_13, DN_20K), /* TRACE_0_DATA4_VNN -- debug header NC */
  30         PAD_NC(GPIO_14, DN_20K), /* TRACE_0_DATA5_VNN -- debug header NC */
  31         PAD_NC(GPIO_15, DN_20K), /* TRACE_0_DATA6_VNN -- debug header NC */
  32         PAD_NC(GPIO_16, DN_20K), /* TRACE_0_DATA7_VNN -- debug header NC */
  33         PAD_NC(GPIO_17, UP_20K), /* DBG_PTI_CLK_1 -- debug header NC */
  34         PAD_NC(GPIO_18, UP_20K), /* DBG_PTI_DATA_8 -- debug header NC */
  35         PAD_NC(GPIO_19, UP_20K), /* DBG_PTI_DATA_9 -- debug header NC */
  36         PAD_NC(GPIO_20, UP_20K), /* DBG_PTI_DATA_10 -- debug header NC */
  37         PAD_CFG_NF(GPIO_21, UP_20K, DEEP, NF2), /* CNV_MFUART2_RXD */
  38         PAD_CFG_NF_IOSSTATE(GPIO_22, UP_20K, DEEP, NF2, TxDRxE), /* CNV_MFUART2_TXD */
  39         PAD_CFG_NF(GPIO_23, UP_20K, DEEP, NF2), /* CNV_GNSS_PABLANKIt */
  40         PAD_NC(GPIO_24, UP_20K), /* TRACE_1_DATA6_VNN -- debug header NC */
  41         PAD_NC(GPIO_25, UP_20K), /* TRACE_1_DATA7_VNN -- debug header NC */
  42         PAD_NC(GPIO_26, DN_20K), /* TRACE_2_CLK_VNN -- debug header NC */
  43         PAD_NC(GPIO_27, DN_20K), /* TRACE_2_DATA0_VNN -- debug header NC */
  44         PAD_NC(GPIO_28, DN_20K), /* TRACE_2_DATA1_VNN 0-- debug header NC */
  45         PAD_NC(GPIO_29, DN_20K), /* TRACE_2_DATA2_VNN -- debug header NC */
  46         PAD_NC(GPIO_30, DN_20K), /* TRACE_2_DATA3_VNN -- debug header NC */
  47         PAD_NC(GPIO_31, DN_20K), /* TRACE_2_DATA4_VNN -- debug header NC */
  48         PAD_NC(GPIO_32, DN_20K), /* TRACE_2_DATA5_VNN -- debug header NC */
  49         PAD_NC(GPIO_33, DN_20K), /* TRACE_2_DATA6_VNN -- debug header NC */
  50         PAD_NC(GPIO_34, DN_20K), /* TRACE_2_DATA7_VNN -- debug header NC */
  51         PAD_NC(GPIO_35, UP_20K), /* TRACE_3_CLK_VNN -- debug header NC */
  52         PAD_NC(GPIO_36, UP_20K), /* TRACE_3_DATA0_VNN -- debug header NC */
  53         PAD_NC(GPIO_37, UP_20K), /* TRACE_3_DATA1_VNN -- debug header NC */
  54         PAD_NC(GPIO_38, UP_20K), /* TRACE_3_DATA2_VNN -- debug header NC */
  55         PAD_NC(GPIO_39, UP_20K), /* TRACE_3_DATA3_VNN -- unused */
  56         PAD_NC(GPIO_40, UP_20K), /* TRACE_3_DATA4_VNN -- unused */
  57         PAD_NC(GPIO_41, DN_20K), /* TRACE_3_DATA5_VNN -- unused */
  58         PAD_NC(GPIO_42, DN_20K), /* GP_INTD_DSI_TE1 -- unused */
  59         PAD_NC(GPIO_43, DN_20K), /* GP_INTD_DSI_TE2 -- debug header NC */
  60         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC0_B */
  61         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* USB_OC1_B */
  62         PAD_NC(GPIO_46, DN_20K), /* DSI_I2C_SDA -- unused */
  63         PAD_NC(GPIO_47, DN_20K), /* DSI_I2C_SCL -- unused */
  64
  65         /* PMC stays active in suspend so disable standby for these pins */
  66         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_48, NONE, DEEP, NF1), /* PMC_I2C_SDA */
  67         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_49, NONE, DEEP, NF1), /* PMC_I2C_SCL */
  68         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SDA */
  69         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* PCH_I2C_PEN_SCL */
  70         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SDA */
  71         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_I2C1_SCL */
  72         PAD_NC(GPIO_54, UP_20K), /* LPSS_I2C2_SDA -- unused */
  73         PAD_NC(GPIO_55, UP_20K), /* LPSS_I2C2_SCL -- unused */
  74         PAD_NC(GPIO_56, UP_20K), /* LPSS_I2C3_SDA -- debug header NC */
  75         PAD_NC(GPIO_57, UP_20K), /* LPSS_I2C2_SCL -- debug header NC */
  76         PAD_NC(GPIO_58, UP_20K), /* LPSS_I2C4_SDA -- unused */
  77         PAD_NC(GPIO_59, UP_20K), /* LPSS_I2C4_SCL -- unused */
  78         PAD_NC(GPIO_60, UP_20K), /* LPSS_UART0_RXD -- debug header NC */
  79         PAD_NC(GPIO_61, UP_20K), /* LPSS_UART0_TXD -- debug header NC */
  80         PAD_NC(GPIO_62, UP_20K), /* UART0-RTS_B -- unused */
  81         PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), /* H1_PCH_INT_ODL */
  82         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
  83         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
  84         PAD_NC(GPIO_66, UP_20K), /* UART2-RTS_B -- unused */
  85         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
  86         PAD_CFG_GPI(GPIO_68, NONE, DEEP), /* DRAM_ID0 */
  87         PAD_CFG_GPI(GPIO_69, NONE, DEEP), /* DRAM_ID1 */
  88         PAD_CFG_GPI(GPIO_70, NONE, DEEP), /* DRAM_ID2 */
  89         PAD_CFG_GPI(GPIO_71, NONE, DEEP), /* DRAM_ID3 */
  90         PAD_NC(GPIO_72, DN_20K), /* PMC_SPI_TXD -- unused */
  91         PAD_NC(GPIO_73, DN_20K), /* PMC_SPI_CLK -- unused */
  92         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_74, UP_20K, DEEP, NF1, TxDRxE, ENPU), /* THERMTRIP_B */
  93         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_75, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PROCHOT_B */
  94         PAD_NC(GPIO_211, UP_20K), /* EMMC_RST_B -- unused */
  95         PAD_CFG_GPI_APIC_IOS(GPIO_212, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* Touch Panel Int */
  96         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_TOUCHSCREEN */
  97         PAD_CFG_GPI_APIC_IOS(GPIO_214, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD), /* P_SENSOR_INT_L */
  98
  99         /* NORTH COMMUNITY GPIOS */
 100
 101         /* svid - unused */
 102         PAD_NC(GPIO_76, UP_20K),/* SVID Alert - unused */
 103         PAD_NC(GPIO_77, UP_20K),/* SVID Data - unused */
 104         PAD_NC(GPIO_78, UP_20K),/* SVID Clk - unused */
 105
 106         /* LPSS */
 107         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_79, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* H1_SLAVE_SPI_CLK_R */
 108         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_80, NONE, DEEP, NF1, HIZCRx1, DISPUPD), /* H1_SLAVE_SPI_CS_L_R */
 109         PAD_NC(GPIO_81, DN_20K), /* GPIO_81_DEBUG -- debug header NC */
 110         PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */
 111         PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */
 112         PAD_NC(GPIO_84, DN_20K), /* LPSS_SPI_2_CLK - unused */
 113         PAD_NC(GPIO_85, DN_20K), /* LPSS_SPI_2_FS0 - unused */
 114         PAD_NC(GPIO_86, DN_20K), /* LPSS_SPI_2_FS1 - unused */
 115         PAD_NC(GPIO_87, DN_20K), /* LPSS_SPI_2_FS2 - unused */
 116         PAD_NC(GPIO_88, DN_20K), /* LPSS_SPI_2_RXD - unused */
 117         PAD_NC(GPIO_89, DN_20K), /* LPSS_SPI_2_TXD - unused */
 118
 119         /* Fast SPI */
 120         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_90, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_CS0_B */
 121         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_91, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD),/* FST_SPI_CS1_B -- SPK_PA_EN_R */
 122         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_92, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MOSI_IO0 */
 123         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_93, NATIVE, DEEP, NF1, HIZCRx1, SAME),/* FST_SPI_MISO_IO1 */
 124         PAD_NC(GPIO_94, NATIVE),/* FST_SPI_IO2 - unused */
 125         PAD_NC(GPIO_95, NATIVE),/* FST_SPI_IO3 - unused */
 126         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_96, NATIVE, DEEP, NF1, HIZCRx0, SAME),/* FST_SPI_CLK */
 127
 128         /* PMU Signals */
 129         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1),/* PMU_PLTRST_B */
 130         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_PWRBTN_B */
 131         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1),/* PMU_SLP_S0_B */
 132         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1),/* PMU_SLP_S3_B */
 133         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1),/* PMU_SLP_S4_B */
 134         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1),/* SUSPWRDNACK */
 135         PAD_NC(GPIO_104, UP_20K),/* EMMC_DNX_PWR_EN_B - unused */
 136         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_105 -- TOUCHSCREEN_RST */
 137         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* PMU_BATLOW_B */
 138         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, NONE, DEEP, NF1, TxDRxE, DISPUPD),/* PMU_RESETBUTTON_B */
 139         PAD_NC(GPIO_108, NONE),/* PMU_SUSCLK -- unused */
 140         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD),/* SUS_STAT_B -- BT_DISABLE_L */
 141
 142         /* I2C5 - Audio */
 143         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SDA */
 144         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C5_SCL */
 145
 146         /* I2C6 - Trackpad */
 147         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SDA */
 148         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C6_SCL */
 149
 150         /* I2C7 - Touchscreen */
 151         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SDA */
 152         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* LPSS_I2C7_SCL */
 153
 154         /* PCIE_WAKE[0:3]_B */
 155         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_116, 1, DEEP, NONE, Tx1RxDCRx1, DISPUPD), /* PCIE_WAKE0_B -- WIFI_DISABLE_L */
 156         PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */
 157         PAD_NC(GPIO_118, UP_20K),/* PCIE_WAKE2_B -- unused */
 158         PAD_CFG_GPI_SCI_LOW(GPIO_119, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE3_B */
 159
 160         /*
 161          * PCIE_CLKREQ[0:3]_B. For unused pins, follow the termination
 162          * guideline for unused PCIE ports as described in PDG i.e. keep
 163          * the pins in native mode and deploy the internal pull up.
 164          */
 165         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ0_B -- unused*/
 166         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ1_B -- unused */
 167         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU),/* PCIE_CLKREQ2_B -- unused */
 168         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, NONE, DEEP, NF1, TxDRxE, DISPUPD), /* PCIE_CLKREQ3_B */
 169
 170         /* DDI[0:1] SDA and SCL -- unused */
 171         PAD_NC(GPIO_124, UP_20K),/* HV_DDI0_DDC_SDA -- unused */
 172         PAD_NC(GPIO_125, UP_20K),/* HV_DDI0_DDC_SCL -- unused */
 173         PAD_NC(GPIO_126, UP_20K),/* HV_DDI1_DDC_SDA -- unused */
 174         PAD_NC(GPIO_127, UP_20K),/* HV_DDI1_DDC_SCL -- unused */
 175
 176         /* Panel 0 control */
 177         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_VDDEN*/
 178         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTEN */
 179         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, NONE, DEEP, NF1, Tx0RxDCRx0, DISPUPD),/* PANEL0_BKLTCTL */
 180
 181         /* Hot plug detect. */
 182         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI0_HPD */
 183         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_DDI1_HPD */
 184         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, HIZCRx1, DISPUPD),/* HV_EDP_HPD */
 185
 186         /* EC_AP_INT_ODL */
 187         PAD_CFG_GPI_APIC_LOW(GPIO_134, NONE, DEEP),
 188
 189         PAD_CFG_GPI_IRQ_WAKE(GPIO_135, NONE, DEEP, LEVEL, INVERT),/* GPIO_135 -- TRACKPAD_INT1_1V8_ODL */
 190         PAD_CFG_GPI_APIC_IOS(GPIO_136, NONE, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD),/* GPIO_136 -- PMIC_PCH_INT_ODL */
 191         PAD_CFG_GPI_APIC_IOS(GPIO_137, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_137 -- HP_INT_ODL */
 192         PAD_CFG_GPI_APIC_IOS(GPIO_138, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_138 -- PEN_PDCT_ODL */
 193         PAD_CFG_GPI_APIC_IOS(GPIO_139, NONE, DEEP, LEVEL, INVERT, HIZCRx1, DISPUPD),/* GPIO_139 -- PEN_INT_ODL */
 194         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_140, 1, DEEP, NONE, Tx1RxDCRx0, DISPUPD),/* GPIO_140 -- PEN_RESET */
 195         // Also we may be able to use eSPI WAKE# Virtual Wire instead
 196         PAD_CFG_GPI_SCI_IOS(GPIO_141, NONE, DEEP, EDGE_SINGLE, INVERT, IGNORE, DISPUPD),/* GPIO_141 -- EC_PCH_WAKE_ODL */
 197         PAD_NC(GPIO_142, UP_20K),/* GPIO_142 -- TRACKPAD_INT2_1V8_ODL(unused) */
 198         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_143, 1, DEEP, UP_20K, HIZCRx1, ENPU),/* GPIO_143 -- LTE_SAR_ODL */
 199
 200         /* GPIO_144 -- PEN_EJECT(wake) */
 201         PAD_CFG_GPI_SCI_HIGH_DEBEN(GPIO_144, UP_20K, DEEP, EDGE_SINGLE,
 202                                                         DEBOUNCE_256_RTC),
 203         /* GPIO_145 -- PEN_EJECT(notifications) */
 204         PAD_CFG_GPI_GPIO_DRIVER(GPIO_145, UP_20K, DEEP),
 205         PAD_NC(GPIO_146, UP_20K),/* GPIO_146 -- unused */
 206
 207         /*
 208          * GPIO_154 - LPC_CLKRUN# has a native function for LPC but not for
 209          * eSPI. Nonetheless if we use eSPI, it should be configured as a GPIO
 210          * and kept unconnected to allow S0ix entry.
 211          */
 212
 213         /* AUDIO COMMUNITY GPIOS*/
 214         PAD_NC(GPIO_156, DN_20K), /* AVS_I2S0_MCLK -- unused */
 215         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_157, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_BCLK */
 216         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_158, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_WS_SYNC */
 217         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_159, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S0_SDI */
 218         PAD_NC(GPIO_160, DN_20K), /* AVS_I2S0_SDO -- unused */
 219         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */
 220         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_162, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_BCLK */
 221         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_163, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_WS_SYNC */
 222         PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
 223         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_165, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_I2S1_SDO */
 224         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_BCLK */
 225         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_WS_SYNC */
 226         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_168, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SDI */
 227         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, NONE, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S2_SD0 */
 228         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF2, HIZCRx0, DISPUPD), /* AVS_I2S1_MCLK */
 229
 230         /* Disable standby for GPIO_171 and GPIO_173 to support Wake on Voice */
 231         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_171, DN_20K, DEEP, NF1), /* AVS_M_CLK_A1 -- DMIC_CLK1 */
 232         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_CLK_B1 */
 233         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_173, DN_20K, DEEP, NF1), /* AVS_M_DATA_1 -- DMIC_DATA */
 234         PAD_NC(GPIO_174, DN_20K), /* AVS_M_CLK_AB2 -- unused */
 235         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* AVS_M_DATA_2 */
 236
 237         /* SCC COMMUNITY GPIOS */
 238         PAD_NC(GPIO_176, UP_20K), /* SMB_ALERTB -- unused */
 239         PAD_NC(GPIO_177, UP_20K), /* SMB_CLK -- unused */
 240         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_178, 0, DEEP, NONE, Tx0RxDCRx0, DISPUPD), /* EN_PP3300_WLAN_L */
 241
 242         PAD_NC(GPIO_179, NONE), /* SDCARD_CLK -- unused */
 243         PAD_NC(GPIO_180, NONE), /* SDCARD_CMD -- unused */
 244         PAD_NC(GPIO_181, UP_20K), /* SDCARD_D0 -- unused */
 245         PAD_NC(GPIO_182, UP_20K), /* SDCARD_D1 -- unused */
 246         PAD_NC(GPIO_183, UP_20K), /* SDCARD_D2 -- unused */
 247         PAD_NC(GPIO_184, UP_20K), /* SDCARD_D3 -- unused */
 248         PAD_NC(GPIO_185, UP_20K), /* SDCARD_CMD -- unused */
 249         PAD_NC(GPIO_186, UP_20K), /* SDCARD_CD_N -- unused */
 250         PAD_NC(GPIO_187, NONE), /* SDCARD_LVL_WP -- unused */
 251         PAD_NC(GPIO_188, UP_20K), /* SDCARD_PWR_DWN_N -- unused */
 252         PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */
 253         PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
 254
 255         /*
 256          * Disable standby state for these CNVI pins to allow wake on
 257          * WiFI & Bluetooth.
 258          */
 259         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_191, NONE, DEEP, NF1), /* CNV_BRI_DT */
 260         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_192, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */
 261         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_193, NONE, DEEP, NF1), /* CNV_RGI_DT */
 262         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_194, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */
 263         PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_195, NONE, DEEP, NF1), /* CNV_RF_RESET_B */
 264         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), /* EMMC0_CLK */
 265         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D0 */
 266         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D1 */
 267         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D2 */
 268         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D3 */
 269         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D4 */
 270         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D5 */
 271         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D6 */
 272         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_D7 */
 273         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), /* EMMC0_CMD */
 274         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, NONE, DEEP, NF1, HIZCRx0, DISPUPD), /* EMMC0_STROBE */
 275         PAD_NC(GPIO_210, DN_20K),
 276 };
 277
 278 const struct pad_config *baseboard_gpio_table(size_t *num)
 279 {
 280         *num = ARRAY_SIZE(gpio_table);
 281         return gpio_table;
 282 }
 283
 284 const struct pad_config *__weak variant_override_gpio_table(size_t *num)
 285 {
 286         *num = 0;
 287         return NULL;
 288 }
 289
 290 const struct pad_config *__weak variant_early_override_gpio_table(size_t *num)
 291 {
 292         *num = 0;
 293         return NULL;
 294 }
 295
 296 static const struct pad_config early_bootblock_gpio_table[] = {
 297         PAD_NC(GPIO_154, NONE), /* LPC_CLKRUNB -- NC for eSPI */
 298         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), /* LPSS_UART2_RXD */
 299         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, TxLASTRxE, DISPUPD), /* LPSS_UART2_TXD */
 300 };
 301
 302 const struct pad_config *mainboard_early_bootblock_gpio_table(size_t *num)
 303 {
 304         *num = ARRAY_SIZE(early_bootblock_gpio_table);
 305         return early_bootblock_gpio_table;
 306 }
 307
 308 /* GPIOs needed prior to ramstage. */
 309 static const struct pad_config early_gpio_table[] = {
 310         PAD_CFG_GPI(GPIO_190, NONE, DEEP), /* PCH_WP_OD */
 311         /* GSPI0_INT */
 312         PAD_CFG_GPI_APIC_IOS(GPIO_63, NONE, DEEP, LEVEL, INVERT, TxDRxE,
 313                 DISPUPD), /* H1_PCH_INT_ODL */
 314         /* GSPI0_CLK */
 315         PAD_CFG_NF(GPIO_79, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CLK_R */
 316         /* GSPI0_CS# */
 317         PAD_CFG_NF(GPIO_80, NONE, DEEP, NF1), /* H1_SLAVE_SPI_CS_L_R */
 318         /* GSPI0_MISO */
 319         PAD_CFG_NF(GPIO_82, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MISO */
 320         /* GSPI0_MOSI */
 321         PAD_CFG_NF(GPIO_83, NONE, DEEP, NF1), /* H1_SLAVE_SPI_MOSI_R */
 322
 323         /* Enable power to wifi early in bootblock and de-assert PERST#. */
 324         PAD_CFG_GPO(GPIO_178, 0, DEEP), /* EN_PP3300_WLAN_L */
 325         PAD_CFG_GPO(GPIO_164, 0, DEEP), /* WLAN_PE_RST */
 326
 327         /*
 328          * ESPI_IO1 acts as ALERT# (which is open-drain) and requires a weak
 329          * pull-up for proper operation. Since there is no external pull present
 330          * on this platform, configure an internal weak pull-up.
 331          */
 332         PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF2, HIZCRx1,
 333                                     ENPU), /* ESPI_IO1 */
 334
 335         /* GPIO_67 and GPIO_117 are in early_gpio_table and gpio_table. For variants
 336          * having LTE SKUs, these two GPIOs would be overridden to output high first
 337          * in the bootblock then be set to default state in gpio_table for non-LTE
 338          * SKUs and keep to output high for LTE SKUs in ramstage.
 339          */
 340         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_67, 0, DEEP, NONE, TxLASTRxE, DISPUPD), /* UART2-CTS_B -- EN_PP3300_DX_LTE_SOC */
 341         PAD_CFG_GPI_SCI_LOW(GPIO_117, NONE, DEEP, EDGE_SINGLE),/* PCIE_WAKE1_B -- LTE_WAKE_L */
 342         /* GPIO_161 is in early_gpio_table and gpio_table because LTE SKU needs
 343          * to override this pin to output low then high respectively in two
 344          * stages.
 345          */
 346         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, UP_20K, Tx1RxDCRx0, DISPUPD), /* AVS_I2S1_MCLK -- LTE_OFF_ODL */
 347
 348         PAD_CFG_GPI(GPIO_189, NONE, DEEP), /* EC_IN_RW */
 349 };
 350
 351 const struct pad_config *__weak
 352 variant_early_gpio_table(size_t *num)
 353 {
 354         *num = ARRAY_SIZE(early_gpio_table);
 355         return early_gpio_table;
 356 }
 357
 358 /* GPIO settings before entering sleep. */
 359 static const struct pad_config sleep_gpio_table[] = {
 360 };
 361
 362 /* GPIO settings before entering slp_s5. */
 363 static const struct pad_config sleep_s5_gpio_table[] = {
 364         /* BT_DISABLE_L */
 365         PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_109, 0, DEEP, NONE, Tx0RxDCRx1, SAME),
 366 };
 367
 368 const struct pad_config *__weak
 369 variant_sleep_gpio_table(size_t *num, int slp_typ)
 370 {
 371         if (slp_typ == ACPI_S5) {
 372                 *num = ARRAY_SIZE(sleep_s5_gpio_table);
 373                 return sleep_s5_gpio_table;
 374         }
 375
 376         *num = ARRAY_SIZE(sleep_gpio_table);
 377         return sleep_gpio_table;
 378 }
 379
 380 const struct pad_config *__weak
 381 variant_romstage_gpio_table(size_t *num)
 382 {
 383         *num = 0;
 384         return NULL;
 385 }
 386
 387 static const struct cros_gpio cros_gpios[] = {
 388         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 389         CROS_GPIO_WP_AH(PAD_SCC(GPIO_PCH_WP), GPIO_COMM_SCC_NAME),
 390 };
 391
 392 DECLARE_WEAK_CROS_GPIOS(cros_gpios);