src/mainboard/google/peach_pit/mainboard.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <arch/cache.h>
   4 #include <boot/coreboot_tables.h>
   5 #include <console/console.h>
   6 #include <device/mmio.h>
   7 #include <delay.h>
   8 #include <device/device.h>
   9 #include <device/i2c_simple.h>
  10 #include <drivers/parade/ps8625/ps8625.h>
  11 #include <ec/google/chromeec/ec.h>
  12 #include <soc/tmu.h>
  13 #include <soc/clk.h>
  14 #include <soc/cpu.h>
  15 #include <soc/gpio.h>
  16 #include <soc/power.h>
  17 #include <soc/periph.h>
  18 #include <soc/i2c.h>
  19 #include <soc/dp.h>
  20 #include <soc/fimd.h>
  21 #include <soc/usb.h>
  22 #include <string.h>
  23 #include <symbols.h>
  24 #include <vbe.h>
  25 #include <framebuffer_info.h>
  26
  27 /* convenient shorthand (in MB) */
  28 #define DRAM_START      ((uintptr_t)_dram/MiB)
  29 #define DRAM_SIZE       CONFIG_DRAM_SIZE_MB
  30
  31 /* from the fdt */
  32 static struct vidinfo vidinfo = {
  33         .vl_freq = 60,
  34         .vl_col = 1366,
  35         .vl_row = 768,
  36         .vl_width = 1366,
  37         .vl_height = 768,
  38         .vl_clkp = 1,
  39         .vl_dp = 1,
  40         .vl_bpix = 4,
  41         .vl_hspw = 32,
  42         .vl_hbpd = 40,
  43         .vl_hfpd = 40,
  44         .vl_vspw = 6,
  45         .vl_vbpd = 10,
  46         .vl_vfpd = 12,
  47         .vl_cmd_allow_len = 0xf,
  48         .win_id = 3,
  49         .dp_enabled = 1,
  50         .dual_lcd_enabled = 0,
  51         .interface_mode = FIMD_RGB_INTERFACE,
  52 };
  53
  54 static unsigned char panel_edid[] = {
  55         0x00,0xff,0xff,0xff,0xff,0xff,0xff,0x00,
  56         0x06,0xaf,0x5c,0x31,0x00,0x00,0x00,0x00,
  57         0x00,0x16,0x01,0x03,0x80,0x1a,0x0e,0x78,
  58         0x0a,0x99,0x85,0x95,0x55,0x56,0x92,0x28,
  59         0x22,0x50,0x54,0x00,0x00,0x00,0x01,0x01,
  60         0x01,0x01,0x01,0x01,0x01,0x01,0x01,0x01,
  61         0x01,0x01,0x01,0x01,0x01,0x01,0xa3,0x1b,
  62         0x56,0x7e,0x50,0x00,0x16,0x30,0x30,0x20,
  63         0x36,0x00,0x00,0x90,0x10,0x00,0x00,0x18,
  64         0x6d,0x12,0x56,0x7e,0x50,0x00,0x16,0x30,
  65         0x30,0x20,0x36,0x00,0x00,0x90,0x10,0x00,
  66         0x00,0x18,0x00,0x00,0x00,0xfe,0x00,0x41,
  67         0x55,0x4f,0x0a,0x20,0x20,0x20,0x20,0x20,
  68         0x20,0x20,0x20,0x20,0x00,0x00,0x00,0xfe,
  69         0x00,0x42,0x31,0x31,0x36,0x58,0x57,0x30,
  70         0x33,0x20,0x56,0x31,0x20,0x0a,0x00,0x3d,
  71         0x00,0xc0,0x00,0x00,0x27,0xfd,0x00,0x20,
  72         0x02,0x59,0x07,0x00,0x64,0x3e,0x07,0x02,
  73         0x00,0x00,0xcd,0x12,0x59,0xff,0x10,0x03,
  74         0x00,0x00,0x00,0x00,0x64,0x00,0x00,0x00,
  75         0x00,0x00,0x00,0x00,0x18,0x00,0x00,0x00,
  76         0x00,0x00,0x00,0x00,0x05,0x00,0x00,0x00,
  77         0x9c,0x3f,0x07,0x02,0x31,0xf9,0x00,0x20,
  78         0x59,0xff,0x10,0x03,0x00,0x00,0x00,0x00,
  79         0xbc,0x3e,0x07,0x02,0xc0,0x9b,0x01,0x20,
  80         0x00,0x00,0x00,0x00,0xdb,0xf8,0x00,0x20,
  81         0x98,0x3e,0x07,0x02,0x8b,0xaf,0x00,0x20,
  82         0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  83         0xe5,0xcd,0x16,0x00,0xe9,0xcd,0x16,0x00,
  84         0xe8,0x03,0x00,0x00,0x6c,0x55,0x01,0x20,
  85         0x2c,0x01,0x00,0x00,0x85,0xbb,0x00,0x20,
  86         0xe8,0x03,0x00,0x00,0xe9,0xcd,0x16,0x00,
  87 };
  88
  89 static const struct parade_write parade_writes[] = {
  90         { 0x02, 0xa1, 0x01 },  /* HPD low */
  91          /*
  92           * SW setting
  93           * [1:0] SW output 1.2V voltage is lower to 96%
  94           */
  95         { 0x04, 0x14, 0x01 },
  96          /*
  97           * RCO SS setting
  98           * [5:4] = b01 0.5%, b10 1%, b11 1.5%
  99           */
 100         { 0x04, 0xe3, 0x20 },
 101         { 0x04, 0xe2, 0x80 }, /* [7] RCO SS enable */
 102          /*
 103           *  RPHY Setting
 104           * [3:2] CDR tune wait cycle before
 105           * measure for fine tune b00: 1us,
 106           * 01: 0.5us, 10:2us, 11:4us.
 107           */
 108         { 0x04, 0x8a, 0x0c },
 109         { 0x04, 0x89, 0x08 }, /* [3] RFD always on */
 110          /*
 111           * CTN lock in/out:
 112           * 20000ppm/80000ppm. Lock out 2
 113           * times.
 114           */
 115         { 0x04, 0x71, 0x2d },
 116          /*
 117           * 2.7G CDR settings
 118           * NOF=40LSB for HBR CDR setting
 119           */
 120         { 0x04, 0x7d, 0x07 },
 121         { 0x04, 0x7b, 0x00 },  /* [1:0] Fmin=+4bands */
 122         { 0x04, 0x7a, 0xfd },  /* [7:5] DCO_FTRNG=+-40% */
 123          /*
 124           * 1.62G CDR settings
 125           * [5:2]NOF=64LSB [1:0]DCO scale is 2/5
 126           */
 127         { 0x04, 0xc0, 0x12 },
 128         { 0x04, 0xc1, 0x92 },  /* Gitune=-37% */
 129         { 0x04, 0xc2, 0x1c },  /* Fbstep=100% */
 130         { 0x04, 0x32, 0x80 },  /* [7] LOS signal disable */
 131          /*
 132           * RPIO Setting
 133           * [7:4] LVDS driver bias current :
 134           * 75% (250mV swing)
 135           */
 136         { 0x04, 0x00, 0xb0 },
 137          /*
 138           * [7:6] Right-bar GPIO output strength is 8mA
 139           */
 140         { 0x04, 0x15, 0x40 },
 141          /* EQ Training State Machine Setting */
 142         { 0x04, 0x54, 0x10 },  /* RCO calibration start */
 143          /* [4:0] MAX_LANE_COUNT set to one lane */
 144         { 0x01, 0x02, 0x81 },
 145          /* [4:0] LANE_COUNT_SET set to one lane */
 146         { 0x01, 0x21, 0x81 },
 147         { 0x00, 0x52, 0x20 },
 148         { 0x00, 0xf1, 0x03 },  /* HPD CP toggle enable */
 149         { 0x00, 0x62, 0x41 },
 150          /* Counter number, add 1ms counter delay */
 151         { 0x00, 0xf6, 0x01 },
 152          /*
 153           * [6]PWM function control by
 154           * DPCD0040f[7], default is PWM
 155           * block always works.
 156           */
 157         { 0x00, 0x77, 0x06 },
 158          /*
 159           * 04h Adjust VTotal tolerance to
 160           * fix the 30Hz no display issue
 161           */
 162         { 0x00, 0x4c, 0x04 },
 163          /* DPCD00400='h00, Parade OUI = 'h001cf8 */
 164         { 0x01, 0xc0, 0x00 },
 165         { 0x01, 0xc1, 0x1c },  /* DPCD00401='h1c */
 166         { 0x01, 0xc2, 0xf8 },  /* DPCD00402='hf8 */
 167          /*
 168           * DPCD403~408 = ASCII code
 169           * D2SLV5='h4432534c5635
 170           */
 171         { 0x01, 0xc3, 0x44 },
 172         { 0x01, 0xc4, 0x32 },  /* DPCD404 */
 173         { 0x01, 0xc5, 0x53 },  /* DPCD405 */
 174         { 0x01, 0xc6, 0x4c },  /* DPCD406 */
 175         { 0x01, 0xc7, 0x56 },  /* DPCD407 */
 176         { 0x01, 0xc8, 0x35 },  /* DPCD408 */
 177          /*
 178           * DPCD40A, Initial Code major  revision
 179           * '01'
 180           */
 181         { 0x01, 0xca, 0x01 },
 182          /* DPCD40B, Initial Code minor revision '05' */
 183         { 0x01, 0xcb, 0x05 },
 184          /* DPCD720, Select external PWM */
 185         { 0x01, 0xa5, 0x80 },
 186          /*
 187           * Set LVDS output as 6bit-VESA mapping,
 188           * single LVDS channel
 189           */
 190         { 0x01, 0xcc, 0x13 },
 191          /* Enable SSC set by register */
 192         { 0x02, 0xb1, 0x20 },
 193          /*
 194           * Set SSC enabled and +/-1% central
 195           * spreading
 196           */
 197         { 0x04, 0x10, 0x16 },
 198          /* MPU Clock source: LC => RCO */
 199         { 0x04, 0x59, 0x60 },
 200         { 0x04, 0x54, 0x14 },  /* LC -> RCO */
 201         { 0x02, 0xa1, 0x91 }  /* HPD high */
 202 };
 203
 204 /* TODO: transplanted DP stuff, clean up once we have something that works */
 205 static enum exynos5_gpio_pin dp_pd_l = GPIO_X35;        /* active low */
 206 static enum exynos5_gpio_pin dp_rst_l = GPIO_Y77;       /* active low */
 207 static enum exynos5_gpio_pin dp_hpd = GPIO_X26;         /* active high */
 208 static enum exynos5_gpio_pin bl_pwm = GPIO_B20;         /* active high */
 209 static enum exynos5_gpio_pin bl_en = GPIO_X22;          /* active high */
 210
 211 static void parade_dp_bridge_setup(void)
 212 {
 213         int i;
 214
 215         gpio_set_value(dp_pd_l, 1);
 216         gpio_cfg_pin(dp_pd_l, GPIO_OUTPUT);
 217         gpio_set_pull(dp_pd_l, GPIO_PULL_NONE);
 218
 219         gpio_set_value(dp_rst_l, 0);
 220         gpio_cfg_pin(dp_rst_l, GPIO_OUTPUT);
 221         gpio_set_pull(dp_rst_l, GPIO_PULL_NONE);
 222         udelay(10);
 223         gpio_set_value(dp_rst_l, 1);
 224
 225         gpio_set_pull(dp_hpd, GPIO_PULL_NONE);
 226         gpio_cfg_pin(dp_hpd, GPIO_INPUT);
 227
 228         /* De-assert PD (and possibly RST) to power up the bridge. */
 229         gpio_set_value(dp_pd_l, 1);
 230         gpio_set_value(dp_rst_l, 1);
 231
 232         /* Hang around for the bridge to come up. */
 233         mdelay(40);
 234
 235         /* Configure the bridge chip. */
 236         exynos_pinmux_i2c7();
 237         i2c_init(7, 100000, 0x00);
 238
 239         parade_ps8625_bridge_setup(7, 0x48, parade_writes,
 240                                    ARRAY_SIZE(parade_writes));
 241         /* Spin until the display is ready.
 242          * It's quite important to try really hard to get the display up,
 243          * so be generous. It will typically be ready in only 5 ms. and
 244          * we're out of here.
 245          * If it's not ready after a second, then we're in big trouble.
 246          */
 247         for (i = 0; i < 1000; i++){
 248                 if (gpio_get_value(dp_hpd))
 249                         break;
 250                 mdelay(1);
 251         }
 252 }
 253
 254 /*
 255  * This delay is T3 in the LCD timing spec (defined as >200ms). We set
 256  * this down to 60ms since that's the approximate maximum amount of time
 257  * it'll take a bridge to start outputting LVDS data. The delay of
 258  * >200ms is just a conservative value to avoid turning on the backlight
 259  * when there's random LCD data on the screen. Shaving 140ms off the
 260  * boot is an acceptable trade-off.
 261  */
 262 #define LCD_T3_DELAY_MS 60
 263
 264 #define LCD_T5_DELAY_MS 10
 265 #define LCD_T6_DELAY_MS 10
 266
 267 static void backlight_pwm(void)
 268 {
 269         /*Configure backlight PWM as a simple output high (100% brightness) */
 270         gpio_direction_output(bl_pwm, 1);
 271         udelay(LCD_T6_DELAY_MS * 1000);
 272 }
 273
 274 static void backlight_en(void)
 275 {
 276         /* Configure GPIO for LCD_BL_EN */
 277         gpio_direction_output(bl_en, 1);
 278 }
 279
 280 static enum exynos5_gpio_pin usb_drd0_vbus = GPIO_H00;
 281 static enum exynos5_gpio_pin usb_drd1_vbus = GPIO_H01;
 282 /* static enum exynos5_gpio_pin hsic_reset_l = GPIO_X24; */
 283
 284 static void prepare_usb(void)
 285 {
 286         /* Kick these resets off early so they get at least 100ms to settle */
 287         reset_usb_drd0_dwc3();
 288         reset_usb_drd1_dwc3();
 289 }
 290
 291 static void setup_usb(void)
 292 {
 293         /* HSIC and USB HOST port not needed in firmware on this board */
 294         setup_usb_drd0_phy();
 295         setup_usb_drd1_phy();
 296
 297         setup_usb_drd0_dwc3();
 298         setup_usb_drd1_dwc3();
 299
 300         gpio_direction_output(usb_drd0_vbus, 1);
 301         gpio_direction_output(usb_drd1_vbus, 1);
 302 }
 303
 304 static struct edp_video_info dp_video_info = {
 305         .master_mode = 0,
 306         .h_sync_polarity        = 0,
 307         .v_sync_polarity        = 0,
 308         .interlaced             = 0,
 309         .color_space            = COLOR_RGB,
 310         .dynamic_range          = VESA,
 311         .ycbcr_coeff            = COLOR_YCBCR601,
 312         .color_depth            = COLOR_8,
 313 };
 314
 315 /* FIXME: move some place more appropriate */
 316 #define MAX_DP_TRIES    5
 317
 318 static void setup_storage(void)
 319 {
 320         /* MMC0: Fixed, 8 bit mode, connected with GPIO. */
 321         if (clock_set_dwmci(PERIPH_ID_SDMMC0))
 322                 printk(BIOS_CRIT, "%s: Failed to set MMC0 clock.\n", __func__);
 323         exynos_pinmux_sdmmc0();
 324
 325         /* MMC2: Removable, 4 bit mode, no GPIO. */
 326         /* (Must be after romstage to avoid breaking SDMMC boot.) */
 327         clock_set_dwmci(PERIPH_ID_SDMMC2);
 328         exynos_pinmux_sdmmc2();
 329 }
 330
 331 static void gpio_init(void)
 332 {
 333         /* Set up the I2C buses. */
 334         exynos_pinmux_i2c2();
 335         exynos_pinmux_i2c4();
 336         exynos_pinmux_i2c7();
 337         exynos_pinmux_i2c8();
 338         exynos_pinmux_i2c9();
 339         exynos_pinmux_i2c10();
 340 }
 341
 342 enum {
 343         FET_CTRL_WAIT = 3 << 2,
 344         FET_CTRL_ADENFET = 1 << 1,
 345         FET_CTRL_ENFET = 1 << 0
 346 };
 347
 348 static void tps65090_thru_ec_fet_set(int index)
 349 {
 350         uint8_t value = FET_CTRL_ADENFET | FET_CTRL_WAIT | FET_CTRL_ENFET;
 351
 352         if (google_chromeec_i2c_xfer(0x48, 0xe + index, 1, &value, 1, 0)) {
 353                 printk(BIOS_ERR,
 354                        "Error sending i2c pass through command to EC.\n");
 355                 return;
 356         }
 357 }
 358
 359 static void lcd_vdd(void)
 360 {
 361         /* Enable FET6, lcd panel */
 362         tps65090_thru_ec_fet_set(6);
 363 }
 364
 365 static void backlight_vdd(void)
 366 {
 367         /* Enable FET1, backlight */
 368         tps65090_thru_ec_fet_set(1);
 369 }
 370
 371 static void sdmmc_vdd(void)
 372 {
 373         /* Enable FET4, P3.3V_SDCARD */
 374         tps65090_thru_ec_fet_set(4);
 375 }
 376
 377 /* this happens after cpu_init where exynos resources are set */
 378 static void mainboard_init(struct device *dev)
 379 {
 380         /* we'll stick with the crummy u-boot struct for now.*/
 381         /* doing this as an auto since the struct has to be writeable */
 382         struct edp_device_info device_info;
 383
 384         void *fb_addr = (void *)(get_fb_base_kb() * KiB);
 385
 386         prepare_usb();
 387         gpio_init();
 388         setup_storage();
 389         tmu_init(&exynos5420_tmu_info);
 390
 391         /* Clock Gating all the unused IP's to save power */
 392         clock_gate();
 393
 394         sdmmc_vdd();
 395
 396         fb_add_framebuffer_info((uintptr_t)fb_addr, 1366, 768, 2 * 1366, 16);
 397
 398         /*
 399          * The reset value for FIMD SYSMMU register MMU_CTRL:0x14640000
 400          * should be 0 according to the datasheet, but has experimentally
 401          * been found to come up as 3. This means FIMD SYSMMU is on by
 402          * default on Exynos5420. For now we are disabling FIMD SYSMMU.
 403          */
 404         write32p(0x14640000, 0x0);
 405         write32p(0x14680000, 0x0);
 406
 407         lcd_vdd();
 408
 409         /* Start the fimd running before you do the phy and lcd setup.
 410          * why do fimd before training etc?
 411          * because we need a data stream from
 412          * the fimd or the clock recovery step fails.
 413          */
 414         vidinfo.screen_base = fb_addr;
 415         exynos_fimd_lcd_init(&vidinfo);
 416
 417         parade_dp_bridge_setup();
 418
 419         /* this might get more dynamic in future ... */
 420         memset(&device_info, 0, sizeof(device_info));
 421         device_info.disp_info.name = (char *)"Peach Pit display";
 422         device_info.disp_info.h_total = 1366;
 423         device_info.disp_info.v_total = 768;
 424         device_info.video_info = dp_video_info;
 425         device_info.raw_edid = panel_edid;
 426         exynos_init_dp(&device_info);
 427
 428         backlight_vdd();
 429         backlight_pwm();
 430         backlight_en();
 431
 432         setup_usb();
 433 }
 434
 435 static void mainboard_enable(struct device *dev)
 436 {
 437         dev->ops->init = &mainboard_init;
 438
 439         /* set up caching for the DRAM */
 440         mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
 441         mmu_config_range((uintptr_t)_dma_coherent/MiB,
 442                          REGION_SIZE(dma_coherent)/MiB, DCACHE_OFF);
 443
 444         const unsigned int epll_hz = 192000000;
 445         const unsigned int sample_rate = 48000;
 446         const unsigned int lr_frame_size = 256;
 447         clock_epll_set_rate(epll_hz);
 448         clock_select_i2s_clk_source();
 449         clock_set_i2s_clk_prescaler(epll_hz, sample_rate * lr_frame_size);
 450
 451         power_enable_xclkout();
 452 }
 453
 454 struct chip_operations mainboard_ops = {
 455         .enable_dev     = mainboard_enable,
 456 };
 457
 458 void lb_board(struct lb_header *header)
 459 {
 460         struct lb_range *dma;
 461
 462         dma = (struct lb_range *)lb_new_record(header);
 463         dma->tag = LB_TAG_DMA;
 464         dma->size = sizeof(*dma);
 465         dma->range_start = (uintptr_t)_dma_coherent;
 466         dma->range_size = REGION_SIZE(dma_coherent);
 467 }