src/mainboard/google/puff/variants/baseboard/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <acpi/acpi.h>
   4 #include <baseboard/gpio.h>
   5 #include <baseboard/variants.h>
   6 #include <types.h>
   7 #include <vendorcode/google/chromeos/chromeos.h>
   8
   9 static const struct pad_config gpio_table[] = {
  10         /* A0  : GPP_A0 ==> NC */
  11         PAD_NC(GPP_A0, NONE),
  12         /* A1  : ESPI_IO0 */
  13         /* A2  : ESPI_IO1 */
  14         /* A3  : ESPI_IO2 */
  15         /* A4  : ESPI_IO3 */
  16         /* A5  : ESPI_CS# */
  17         /* A6  : GPP_A6 ==> NC */
  18         PAD_NC(GPP_A6, NONE),
  19         /* A7  : PP3300_SOC_A */
  20         PAD_NC(GPP_A7, NONE),
  21         /* A8  : GPP_A8 ==> NC */
  22         PAD_NC(GPP_A8, NONE),
  23         /* A9  : ESPI_CLK */
  24         /* A10  : GPP_A10 ==> NC */
  25         PAD_NC(GPP_A10, NONE),
  26         /* A11  : GPP_A11 ==> NC */
  27         PAD_NC(GPP_A11, NONE),
  28         /* A12  : GPP_A12 ==> NC */
  29         PAD_NC(GPP_A12, NONE),
  30         /* A13 : SUSWARN_L */
  31         PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
  32         /* A14 : ESPI_RST_L */
  33         /* A15 : SUSACK_L */
  34         PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
  35         /* A16 : SD_1P8_SEL => NC */
  36         PAD_NC(GPP_A16, NONE),
  37         /* A17 : EN_PP3300_SD_DX */
  38         PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
  39         /* A18 : EN_PP3300_WWAN */
  40         PAD_CFG_GPO(GPP_A18, 1, DEEP),
  41         /* A19 : WWAN_RADIO_DISABLE_1V8_ODL */
  42         PAD_CFG_GPO(GPP_A19, 1, DEEP),
  43         /* A20 : WLAN_INT_L */
  44         PAD_CFG_GPI_APIC(GPP_A20, NONE, PLTRST, LEVEL, INVERT),
  45         /* A21 : TRACKPAD_INT_ODL */
  46         PAD_CFG_GPI_IRQ_WAKE(GPP_A21, NONE, DEEP, LEVEL, INVERT),
  47         /* A22 : FPMCU_PCH_BOOT0 */
  48         PAD_CFG_GPO(GPP_A22, 0, DEEP),
  49         /* A23 : FPMCU_PCH_INT_ODL */
  50         PAD_CFG_GPI_IRQ_WAKE(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
  51
  52         /* B0  : CORE_VID0 */
  53         PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1),
  54         /* B1  : CORE_VID1 */
  55         PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1),
  56         /* B2  : GPP_B2 ==> NC */
  57         PAD_NC(GPP_B2, NONE),
  58         /* B3  : GPP_B3 ==> NC */
  59         PAD_NC(GPP_B3, NONE),
  60         /* B4  : GPP_B4 ==> NC */
  61         PAD_NC(GPP_B4, NONE),
  62         /* B5  : GPP_B5 ==> NC */
  63         PAD_NC(GPP_B5, NONE),
  64         /* B6  : SRCCLKREQ1 */
  65         PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
  66         /* B7  : GPP_B7 ==> NC */
  67         PAD_NC(GPP_B7, NONE),
  68         /* B8  : PCIE_14_WLAN_CLKREQ_ODL */
  69         PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
  70         /* B9  : GPP_B9 ==> NC */
  71         PAD_NC(GPP_B9, NONE),
  72         /* B10 : GPP_B10 ==> NC */
  73         PAD_NC(GPP_B10, NONE),
  74         /* B11 : EXT_PWR_GATE_L */
  75         PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
  76         /* B12 : SLP_S0_L */
  77         PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  78         /* B13 : PLT_RST_L */
  79         PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  80         /* B14 : GPP_B14_STRAP */
  81         PAD_NC(GPP_B14, NONE),
  82         /* B15 : H1_SLAVE_SPI_CS_L */
  83         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
  84         /* B16 : H1_SLAVE_SPI_CLK */
  85         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
  86         /* B17 : H1_SLAVE_SPI_MISO_R */
  87         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
  88         /* B18 : H1_SLAVE_SPI_MOSI_R */
  89         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
  90         /* B19 : Set to NF1 to match FSP setting it to NF1, i.e., GSPI1_CS0# */
  91         PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
  92         /* B20 : PCH_SPI_FPMCU_CLK_R */
  93         PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
  94         /* B21 : PCH_SPI_FPMCU_MISO */
  95         PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
  96         /* B22 : PCH_SPI_FPMCU_MOSI */
  97         PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
  98         /* B23 : GPP_B23_STRAP */
  99         PAD_NC(GPP_B23, NONE),
 100
 101         /* C0  : GPP_C0 => NC */
 102         PAD_NC(GPP_C0, NONE),
 103         /* C1  : PCIE_14_WLAN_WAKE_ODL */
 104         PAD_CFG_GPI_SCI_LOW(GPP_C1, NONE, DEEP, EDGE_SINGLE),
 105         /* C2  : GPP_C2 => NC */
 106         PAD_NC(GPP_C2, NONE),
 107         /* C3  : WLAN_OFF_L */
 108         PAD_CFG_GPO(GPP_C3, 1, DEEP),
 109         /* C4  : TOUCHSCREEN_DIS_L */
 110         PAD_CFG_GPO(GPP_C4, 1, DEEP),
 111         /* C5  : GPP_C5 => NC */
 112         PAD_NC(GPP_C5, NONE),
 113         /* C6  : PEN_PDCT_OD_L */
 114         PAD_NC(GPP_C6, NONE),
 115         /* C7  : PEN_IRQ_OD_L */
 116         PAD_NC(GPP_C7, NONE),
 117         /* C8  : UART_PCH_RX_DEBUG_TX */
 118         PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
 119         /* C9  : UART_PCH_TX_DEBUG_RX */
 120         PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 121         /* C10 : GPP_10 ==> GPP_C10_TP */
 122         PAD_NC(GPP_C10, NONE),
 123         /* C11 : GPP_11 ==> EN_FP_RAILS */
 124         PAD_CFG_GPO(GPP_C11, 0, DEEP),
 125         /* C12 : GPP_C12 ==> NC */
 126         PAD_NC(GPP_C12, NONE),
 127         /* C13 : EC_PCH_INT_L */
 128         PAD_CFG_GPI_APIC(GPP_C13, NONE, PLTRST, LEVEL, INVERT),
 129         /* C14 : BT_DISABLE_L */
 130         PAD_CFG_GPO(GPP_C14, 1, DEEP),
 131         /* C15 : NC */
 132         PAD_NC(GPP_C15, NONE),
 133         /* C16 : PCH_I2C_TRACKPAD_SDA */
 134         PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1),
 135         /* C17 : PCH_I2C_TRACKPAD_SCL */
 136         PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1),
 137         /* C18 : PCH_I2C_TOUCHSCREEN_SDA */
 138         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
 139         /* C19 : PCH_I2C_TOUCHSCREEN_SCL */
 140         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
 141         /* C20 : PCH_WP_OD */
 142         PAD_CFG_GPI(GPP_C20, NONE, DEEP),
 143         /* C21 : H1_PCH_INT_ODL */
 144         PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
 145         /* C22 : EC_IN_RW_OD */
 146         PAD_CFG_GPI(GPP_C22, NONE, DEEP),
 147         /* C23 : WLAN_PE_RST# */
 148         PAD_CFG_GPO(GPP_C23, 1, DEEP),
 149
 150         /* D0  : TP31 */
 151         PAD_NC(GPP_D0, NONE),
 152         /* D1  : TP16 */
 153         PAD_NC(GPP_D1, NONE),
 154         /* D2  : TP26 */
 155         PAD_NC(GPP_D2, NONE),
 156         /* D3  : TP27 */
 157         PAD_NC(GPP_D3, NONE),
 158         /* D4  : TP40 */
 159         PAD_NC(GPP_D4, NONE),
 160         /* D5  : WWAN_CONFIG_0 */
 161         PAD_NC(GPP_D5, NONE),
 162         /* D6  : WWAN_CONFIG_1 */
 163         PAD_NC(GPP_D6, NONE),
 164         /* D7  : WWAN_CONFIG_2 */
 165         PAD_NC(GPP_D7, NONE),
 166         /* D8  : WWAN_CONFIG_3 */
 167         PAD_NC(GPP_D8, NONE),
 168         /* D9  : GPP_D9 ==> EN_PP3300_DX_TOUCHSCREEN */
 169         PAD_CFG_GPO(GPP_D9, 0, DEEP),
 170         /* D10 : GPP_D10 ==> NC */
 171         PAD_NC(GPP_D10, NONE),
 172         /* D11 : GPP_D11 ==> NC */
 173         PAD_NC(GPP_D11, NONE),
 174         /* D12 : GPP_D12 */
 175         PAD_NC(GPP_D12, NONE),
 176         /* D13 : ISH_UART_RX */
 177         PAD_NC(GPP_D13, NONE),
 178         /* D14 : ISH_UART_TX */
 179         PAD_NC(GPP_D14, NONE),
 180         /* D15 : TOUCHSCREEN_RST_L */
 181         PAD_CFG_GPO(GPP_D15, 0, DEEP),
 182         /* D16 : USI_INT */
 183         PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, NONE),
 184         /* D17 : PCH_HP_SDW_CLK */
 185         PAD_NC(GPP_D17, NONE),
 186         /* D18 : PCH_HP_SDW_DAT */
 187         PAD_NC(GPP_D18, NONE),
 188         /* D19 : DMIC_CLK_0_SNDW4_CLK */
 189         PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
 190         /* D20 : DMIC_DATA_0_SNDW4_DATA */
 191         PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
 192         /* D21 : GPP_D21 ==> NC */
 193         PAD_NC(GPP_D21, NONE),
 194         /* D22 : GPP_D22 ==> NC */
 195         PAD_NC(GPP_D22, NONE),
 196         /* D23 : SPP_MCLK */
 197         PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
 198
 199         /* E0  : GPP_E0 ==> NC */
 200         PAD_NC(GPP_E0, NONE),
 201         /* E1  : M2_SSD_PEDET */
 202         PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 203         /* E2  : GPP_E2 ==> NC */
 204         PAD_NC(GPP_E2, NONE),
 205         /* E3  : GPP_E3 ==> NC */
 206         PAD_NC(GPP_E3, NONE),
 207         /* E4  : M2_SSD_PE_WAKE_ODL */
 208         PAD_CFG_GPI(GPP_E4, NONE, DEEP),
 209         /* E5  : SATA_DEVSLP1 */
 210         PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
 211         /* E6  : M2_SSD_RST_L */
 212         PAD_NC(GPP_E6, NONE),
 213         /* E7  : GPP_E7 ==> NC */
 214         PAD_NC(GPP_E7, NONE),
 215         /* E8  : GPP_E8 ==> NC */
 216         PAD_NC(GPP_E8, NONE),
 217         /* E9  : GPP_E9 ==> NC */
 218         PAD_NC(GPP_E9, NONE),
 219         /* E10 : GPP_E10 ==> NC */
 220         PAD_NC(GPP_E10, NONE),
 221         /* E11 : USB_C_OC_OD USB_OC2 */
 222         PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
 223         /* E12 : USB_A_OC_OD USB_OC3 */
 224         PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
 225         /* E13 : USB_C0_DP_HPD */
 226         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
 227         /* E14 : DDI2_HPD_ODL */
 228         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
 229         /* E15 : DDPD_HPD2 =>  NC */
 230         PAD_NC(GPP_E15, NONE),
 231         /* E16 : DDPE_HPD2 => NC */
 232         PAD_NC(GPP_E16, NONE),
 233         /* E17 : EDP_HPD */
 234         PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 235         /* E18 : DDPB_CTRLCLK => NC */
 236         PAD_NC(GPP_E18, NONE),
 237         /* E19 : GPP_E19_STRAP */
 238         PAD_CFG_GPI(GPP_E19, NONE, DEEP),
 239         /* E20 : DDPC_CTRLCLK => NC */
 240         PAD_NC(GPP_E20, NONE),
 241         /* E21 : GPP_E21_STRAP */
 242         PAD_CFG_GPI(GPP_E21, NONE, DEEP),
 243         /* E22 : DDPD_CTRLCLK => NC */
 244         PAD_NC(GPP_E22, NONE),
 245         /* E23 : GPP_E23_STRAP */
 246         PAD_NC(GPP_E23, NONE),
 247
 248         /* F0  : GPIO_WWAN_WLAN_COEX3 */
 249         PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1),
 250         /* F1  : WWAN_RESET_1V8_ODL */
 251         PAD_CFG_GPO(GPP_F1, 1, DEEP),
 252         /* F2  : MEM_CH_SEL */
 253         PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
 254         /* F3  : GPP_F3 ==> NC */
 255         PAD_NC(GPP_F3, NONE),
 256         /* F4  : CNV_BRI_DT */
 257         PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 258         /* F5  : CNV_BRI_RSP */
 259         PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
 260         /* F6  : CNV_RGI_DT */
 261         PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
 262         /* F7  : CNV_RGI_RSP */
 263         PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
 264         /* F8  : UART_WWANTX_WLANRX_COEX1 */
 265         PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
 266         /* F9  : UART_WWANRX_WLANTX_COEX2 */
 267         PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
 268         /* F10 : GPP_F10 ==> NC */
 269         PAD_NC(GPP_F10, NONE),
 270         /* F11 : PCH_MEM_STRAP2 */
 271         PAD_CFG_GPI(GPP_F11, NONE, PLTRST),
 272         /* F12 : GPP_F12 ==> NC */
 273         PAD_NC(GPP_F12, NONE),
 274         /* F13 : GPP_F13 ==> NC */
 275         PAD_NC(GPP_F13, NONE),
 276         /* F14 : GPP_F14 ==> NC */
 277         PAD_NC(GPP_F14, NONE),
 278         /* F15 : GPP_F15 ==> NC */
 279         PAD_NC(GPP_F15, NONE),
 280         /* F16 : GPP_F16 ==> NC */
 281         PAD_NC(GPP_F16, NONE),
 282         /* F17 : GPP_F17 ==> NC */
 283         PAD_NC(GPP_F17, NONE),
 284         /* F18 : GPP_F18 ==> NC */
 285         PAD_NC(GPP_F18, NONE),
 286         /* F19 : GPP_F19 ==> NC */
 287         PAD_NC(GPP_F19, NONE),
 288         /* F20 : PCH_MEM_STRAP0 */
 289         PAD_CFG_GPI(GPP_F20, NONE, PLTRST),
 290         /* F21 : PCH_MEM_STRAP1 */
 291         PAD_CFG_GPI(GPP_F21, NONE, PLTRST),
 292         /* F22 : PCH_MEM_STRAP3 */
 293         PAD_CFG_GPI(GPP_F22, NONE, PLTRST),
 294         /* F23 : GPP_F23 ==> NC */
 295         PAD_NC(GPP_F23, NONE),
 296
 297         /* G0  : SD_CMD */
 298         PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1),
 299         /* G1  : SD_DATA0 */
 300         PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1),
 301         /* G2  : SD_DATA1 */
 302         PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1),
 303         /* G3  : SD_DATA2 */
 304         PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1),
 305         /* G4  : SD_DATA3 */
 306         PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1),
 307         /* G5  : SD_CD# */
 308         PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1),
 309         /* G6  : SD_CLK */
 310         PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
 311         /* G7  : SD_WP
 312          * As per schematics SD host controller SD_WP pin is not connected to
 313          * uSD card connector. In order to overcome gpio default state, ensures
 314          * to configure gpio pin as NF1 with internal 20K pull down.
 315          */
 316         PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1),
 317         /*
 318          * H0  : HP_INT_L
 319          */
 320         PAD_CFG_GPI_INT(GPP_H0, NONE, PLTRST, EDGE_BOTH),
 321         /* H1  : CNV_RF_RESET_L */
 322         PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3),
 323         /* H2  : CNV_CLKREQ0 */
 324         PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3),
 325         /* H3 : GPP_H3 ==> NC */
 326         PAD_NC(GPP_H3, NONE),
 327         /* H4  : PCH_I2C_PEN_SDA */
 328         PAD_NC(GPP_H4, NONE),
 329         /* H5  : PCH_I2C_PEN_SCL */
 330         PAD_NC(GPP_H5, NONE),
 331         /* H6  : PCH_I2C_SAR0_MST_SDA */
 332         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 333         /* H7  : PCH_I2C_SAR0_MST_SCL */
 334         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 335         /* H8  : PCH_I2C_M2_AUDIO_SAR1_SDA */
 336         PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1),
 337         /* H9  : PCH_I2C_M2_AUDIO_SAR1_SCL */
 338         PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1),
 339         /* H10 : PCH_I2C_TRACKPAD_SDA */
 340         PAD_NC(GPP_H10, NONE),
 341         /* H11 : PCH_I2C_TRACKPAD_SCL */
 342         PAD_NC(GPP_H11, NONE),
 343         /* H12 : GPP_H12 ==> NC */
 344         PAD_NC(GPP_H12, NONE),
 345         /* H13 : GPP_H13 ==> NC */
 346         PAD_NC(GPP_H13, NONE),
 347         /* H14 : GPP_H14 ==> NC */
 348         PAD_NC(GPP_H14, NONE),
 349         /* H15 : GPP_H15 ==> NC */
 350         PAD_NC(GPP_H15, NONE),
 351         /* H16 : GPP_H16 ==> NC */
 352         PAD_NC(GPP_H16, NONE),
 353         /* H17 : TP1 */
 354         PAD_NC(GPP_H17, NONE),
 355         /* H18 : CPU_C10_GATE_L */
 356         PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1),
 357         /* H19 : GPP_H19 ==> NC */
 358         PAD_NC(GPP_H19, NONE),
 359         /* H20 : TP41 */
 360         PAD_NC(GPP_H20, NONE),
 361         /* H21 : XTAL_FREQ_SEL */
 362         PAD_NC(GPP_H21, NONE),
 363         /* H22 : GPP_H22 ==> NC */
 364         PAD_NC(GPP_H22, NONE),
 365         /* H23 : GPP_H23_STRAP */
 366         PAD_NC(GPP_H23, NONE),
 367
 368         /* GPD2: LAN_WAKE# ==> EC_PCH_WAKE_ODL */
 369         PAD_CFG_NF(GPD2, NONE, DEEP, NF1),
 370
 371         /* SD card detect VGPIO */
 372         PAD_CFG_GPI_GPIO_DRIVER(vSD3_CD_B, NONE, DEEP),
 373
 374         /* CNV_WCEN  : Disable Wireless Charging */
 375         PAD_CFG_GPO(CNV_WCEN, 0, DEEP),
 376 };
 377
 378 const struct pad_config *base_gpio_table(size_t *num)
 379 {
 380         *num = ARRAY_SIZE(gpio_table);
 381         return gpio_table;
 382 }
 383
 384 /*
 385  * Default GPIO settings before entering non-S5 sleep states.
 386  * Configure A12: FPMCU_RST_ODL as GPO before entering sleep.
 387  * This guarantees that A12's native3 function is disabled.
 388  * See https://review.coreboot.org/c/coreboot/+/32111 .
 389  */
 390 static const struct pad_config default_sleep_gpio_table[] = {
 391         PAD_CFG_GPO(GPP_A12, 1, DEEP), /* FPMCU_RST_ODL */
 392 };
 393
 394 /*
 395  * GPIO settings before entering S5, which are same as
 396  * default_sleep_gpio_table but also,
 397  * turn off EN_PP3300_WWAN and FPMCU.
 398  */
 399 static const struct pad_config s5_sleep_gpio_table[] = {
 400         PAD_CFG_GPO(GPP_A12, 0, DEEP), /* FPMCU_RST_ODL */
 401         PAD_CFG_GPO(GPP_C11, 0, DEEP), /* PCH_FP_PWR_EN */
 402         PAD_CFG_GPO(GPP_A18, 0, DEEP), /* EN_PP3300_WWAN */
 403 };
 404
 405 const struct pad_config *__weak variant_sleep_gpio_table(
 406         u8 slp_typ, size_t *num)
 407 {
 408         if (slp_typ == ACPI_S5) {
 409                 *num = ARRAY_SIZE(s5_sleep_gpio_table);
 410                 return s5_sleep_gpio_table;
 411         }
 412         *num = ARRAY_SIZE(default_sleep_gpio_table);
 413         return default_sleep_gpio_table;
 414 }
 415
 416 static const struct cros_gpio cros_gpios[] = {
 417         CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
 418         CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
 419 };
 420
 421 DECLARE_WEAK_CROS_GPIOS(cros_gpios);
 422
 423 /* Weak implementation of overrides */
 424 const struct pad_config *__weak override_gpio_table(size_t *num)
 425 {
 426         *num = 0;
 427         return NULL;
 428 }
 429
 430 /* Weak implementation of early gpio */
 431 const struct pad_config *__weak variant_early_gpio_table(size_t *num)
 432 {
 433         *num = 0;
 434         return NULL;
 435 }