src/mainboard/google/puff/variants/dooly/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6
   7 static const struct pad_config gpio_table[] = {
   8         /* A17 : SD_VDD1_PWR_EN */
   9         PAD_NC(GPP_A17, NONE),
  10         /* A18 : GPP_A18 */
  11         PAD_NC(GPP_A18, NONE),
  12         /* A19 : GPP_A19 */
  13         PAD_NC(GPP_A19, NONE),
  14         /* A20 : TOUCH_INT_ODL */
  15         PAD_CFG_GPI_IRQ_WAKE(GPP_A20, NONE, PLTRST, LEVEL, INVERT),
  16         /* A21 : FPMCU_PCH_BOOT0 */
  17         PAD_NC(GPP_A21, NONE),
  18         /* A22 : FPMCU_PCH_INT_L */
  19         PAD_NC(GPP_A22, NONE),
  20         /* A23 : M2_WLAN_INT_ODL */
  21         PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
  22
  23         /* C0 : SMBCLK */
  24         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
  25         /* C1 : SMBDATA */
  26         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
  27         /* C3  : GPP_C3 */
  28         PAD_NC(GPP_C3, NONE),
  29         /* C4  : GPP_C4 */
  30         PAD_NC(GPP_C4, NONE),
  31         /* C6: M2_WLAN_WAKE_ODL */
  32         PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE),
  33         /* C7 : LAN_WAKE_ODL */
  34         PAD_NC(GPP_C7, NONE),
  35         /* C11 : GPP_C11 */
  36         PAD_NC(GPP_C11, NONE),
  37         /* C15  : WLAN_OFF_L */
  38         PAD_CFG_GPO(GPP_C15, 1, DEEP),
  39         /* C18 : GPP_C18 */
  40         PAD_NC(GPP_C18, NONE),
  41         /* C19 : GPP_C19 */
  42         PAD_NC(GPP_C19, NONE),
  43
  44         /* D16 : DMIC_ON_OFF MIC_SWITCH_L */
  45         PAD_CFG_GPI_GPIO_DRIVER(GPP_D16, NONE, DEEP),
  46
  47         /* E2  : EN_PP_MST_OD */
  48         PAD_CFG_GPO(GPP_E2, 1, DEEP),
  49
  50         /* F0 : GPP_F0 */
  51         PAD_NC(GPP_F0, NONE),
  52         /* F1 : GPP_F1 */
  53         PAD_NC(GPP_F1, NONE),
  54         /* F8 : GPP_F8 */
  55         PAD_NC(GPP_F8, NONE),
  56         /* F9 : GPP_F9 */
  57         PAD_NC(GPP_F9, NONE),
  58         /* F11 : EMMC_CMD */
  59         PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
  60         /* F12 : EMMC_DATA0 */
  61         PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
  62         /* F13 : EMMC_DATA1 */
  63         PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
  64         /* F14 : EMMC_DATA2 */
  65         PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
  66         /* F15 : EMMC_DATA3 */
  67         PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
  68         /* F16 : EMMC_DATA4 */
  69         PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
  70         /* F17 : EMMC_DATA5 */
  71         PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
  72         /* F18 : EMMC_DATA6 */
  73         PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
  74         /* F19 : EMMC_DATA7 */
  75         PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
  76         /* F20 : EMMC_RCLK */
  77         PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
  78         /* F21 : EMMC_CLK */
  79         PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
  80         /* F22 : EMMC_RST_L */
  81         PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
  82
  83         /* G0  : SD_CMD */
  84         PAD_NC(GPP_G0, NONE),
  85         /* G1  : SD_DATA0 */
  86         PAD_NC(GPP_G1, NONE),
  87         /* G2  : SD_DATA1 */
  88         PAD_NC(GPP_G2, NONE),
  89         /* G3  : SD_DATA2 */
  90         PAD_NC(GPP_G3, NONE),
  91         /* G4  : SD_DATA3 */
  92         PAD_NC(GPP_G4, NONE),
  93         /* G5  : SD_CD */
  94         PAD_NC(GPP_G5, NONE),
  95         /* G6  : SD_CLK */
  96         PAD_NC(GPP_G6, NONE),
  97
  98         /* H3  : SPK_AMP_ON */
  99         PAD_CFG_GPO(GPP_H3, 1, DEEP),
 100         /* H4: LVDS_SDA */
 101         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 102         /* H5: LVDS_SDL */
 103         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 104         /* H6 : PCH_I2C_TOUCH_SDA */
 105         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 106         /* H7 : PCH_I2C_TOUCH_SDL */
 107         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 108 };
 109
 110 const struct pad_config *override_gpio_table(size_t *num)
 111 {
 112         *num = ARRAY_SIZE(gpio_table);
 113         return gpio_table;
 114 }
 115
 116 /* Early pad configuration in bootblock */
 117 static const struct pad_config early_gpio_table[] = {
 118         /* B14 : GPP_B14_STRAP */
 119         PAD_NC(GPP_B14, NONE),
 120         /* B22 : GPP_B22_STRAP */
 121         PAD_NC(GPP_B22, NONE),
 122         /* E19 : GPP_E19_STRAP */
 123         PAD_NC(GPP_E19, NONE),
 124         /* E21 : GPP_E21_STRAP */
 125         PAD_NC(GPP_E21, NONE),
 126         /* B15 : H1_SLAVE_SPI_CS_L */
 127         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 128         /* B16 : H1_SLAVE_SPI_CLK */
 129         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
 130         /* B17 : H1_SLAVE_SPI_MISO_R */
 131         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 132         /* B18 : H1_SLAVE_SPI_MOSI_R */
 133         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 134         /* C8  : UART_PCH_RX_DEBUG_TX */
 135         PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
 136         /* C9  : UART_PCH_TX_DEBUG_RX */
 137         PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 138         /* C14 : BT_DISABLE_L */
 139         PAD_CFG_GPO(GPP_C14, 0, DEEP),
 140         /* PCH_WP_OD */
 141         PAD_CFG_GPI(GPP_C20, NONE, DEEP),
 142         /* C21 : H1_PCH_INT_ODL */
 143         PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
 144         /* C22 : EC_IN_RW_OD */
 145         PAD_CFG_GPI(GPP_C22, NONE, DEEP),
 146         /* C23 : WLAN_PE_RST# */
 147         PAD_CFG_GPO(GPP_C23, 1, DEEP),
 148         /* E1  : M2_SSD_PEDET */
 149         PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 150         /* E5  : SATA_DEVSLP1 */
 151         PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
 152 };
 153
 154 const struct pad_config *variant_early_gpio_table(size_t *num)
 155 {
 156         *num = ARRAY_SIZE(early_gpio_table);
 157         return early_gpio_table;
 158 }