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mainboard/intel/avenuecity_crb: Update full IIO configuration
[coreboot2.git] / src / mainboard / google / puff / variants / dooly / overridetree.cb
blobfce8eec27335df318c715ffe9655bb1e4c8c560b
1 fw_config
2 field AUDIO_CODEC_SOURCE 8 10
3 option AUDIO_CODEC_UNPROVISIONED 0
4 option AUDIO_CODEC_ALC5682 1
5 option AUDIO_CODEC_ALC5682I_VS 2
6 end
7 end
8
9 chip soc/intel/cannonlake
10
11 register "power_limits_config" = "{
12 .tdp_pl1_override = 25,
13 .tdp_pl2_override = 49,
14 }"
15
16 # Auto-switch between X4 NVMe and X2 NVMe.
17 register "TetonGlacierMode" = "1"
18
19 register "SerialIoDevMode" = "{
20 [PchSerialIoIndexI2C0] = PchSerialIoPci,
21 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
22 [PchSerialIoIndexI2C2] = PchSerialIoPci,
23 [PchSerialIoIndexI2C3] = PchSerialIoPci,
24 [PchSerialIoIndexI2C4] = PchSerialIoPci,
25 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
26 [PchSerialIoIndexSPI0] = PchSerialIoPci,
27 [PchSerialIoIndexSPI1] = PchSerialIoDisabled,
28 [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
29 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
30 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
31 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
32 }"
33
34 # USB configuration
35 register "usb2_ports[0]" = "{
36 .enable = 1,
37 .ocpin = OC2,
38 .tx_bias = USB2_BIAS_0MV,
39 .tx_emp_enable = USB2_PRE_EMP_ON,
40 .pre_emp_bias = USB2_BIAS_11P25MV,
41 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
42 }" # Type-A Port 0
43 register "usb2_ports[1]" = "{
44 .enable = 1,
45 .ocpin = OC_SKIP,
46 .tx_bias = USB2_BIAS_0MV,
47 .tx_emp_enable = USB2_PRE_EMP_ON,
48 .pre_emp_bias = USB2_BIAS_28P15MV,
49 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
50 }" # Type-C Port 0
51 register "usb2_ports[2]" = "{
52 .enable = 1,
53 .ocpin = OC3,
54 .tx_bias = USB2_BIAS_0MV,
55 .tx_emp_enable = USB2_PRE_EMP_ON,
56 .pre_emp_bias = USB2_BIAS_28P15MV,
57 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
58 }" # Type-A Port 1
59 register "usb2_ports[3]" = "USB2_PORT_EMPTY"
60 register "usb2_ports[4]" = "{
61 .enable = 1,
62 .ocpin = OC_SKIP,
63 .tx_bias = USB2_BIAS_0MV,
64 .tx_emp_enable = USB2_PRE_EMP_ON,
65 .pre_emp_bias = USB2_BIAS_28P15MV,
66 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
67 }" # Type-C Port 1
68 register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam
69 register "usb2_ports[6]" = "USB2_PORT_EMPTY"
70 register "usb2_ports[7]" = "USB2_PORT_EMPTY"
71 register "usb2_ports[8]" = "USB2_PORT_EMPTY"
72 register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT
73
74 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
75 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1
76 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 1
77 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C Port 0
78 register "usb3_ports[4]" = "USB3_PORT_EMPTY"
79 register "usb3_ports[5]" = "USB3_PORT_EMPTY"
80
81 # Bitmap for Wake Enable on USB attach/detach
82 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
83 USB_PORT_WAKE_ENABLE(3)"
84 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
85 USB_PORT_WAKE_ENABLE(2)"
86
87 # Enable eMMC HS400
88 register "ScsEmmcHs400Enabled" = "1"
89
90 # EMMC Tx CMD Delay
91 # Refer to EDS-Vol2-14.3.7.
92 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
93 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
94 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
95
96 # EMMC TX DATA Delay 1
97 # Refer to EDS-Vol2-14.3.8.
98 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
99 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
100 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
101
102 # EMMC TX DATA Delay 2
103 # Refer to EDS-Vol2-14.3.9.
104 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
105 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
106 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
107 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
108 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
109
110 # EMMC RX CMD/DATA Delay 1
111 # Refer to EDS-Vol2-14.3.10.
112 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
113 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
114 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
115 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
116 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
117
118 # EMMC RX CMD/DATA Delay 2
119 # Refer to EDS-Vol2-14.3.12.
120 # [17:16] stands for Rx Clock before Output Buffer,
121 # 00: Rx clock after output buffer,
122 # 01: Rx clock before output buffer,
123 # 10: Automatic selection based on working mode.
124 # 11: Reserved
125 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
126 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
127 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
128
129 # EMMC Rx Strobe Delay
130 # Refer to EDS-Vol2-14.3.11.
131 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
132 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
133 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
134
135 # Intel Common SoC Config
136 #+-------------------+---------------------------+
137 #| Field | Value |
138 #+-------------------+---------------------------+
139 #| GSPI0 | cr50 TPM. Early init is |
140 #| | required to set up a BAR |
141 #| | for TPM communication |
142 #| | before memory is up |
143 #| I2C0 | ALC 1015 |
144 #| I2C2 | Lvds |
145 #| I2C3 | Touchscreen |
146 #| I2C4 | RT5682 |
147 #+-------------------+---------------------------+
148 register "common_soc_config" = "{
149 .gspi[0] = {
150 .speed_mhz = 1,
151 .early_init = 1,
152 },
153 .i2c[0] = {
154 .speed = I2C_SPEED_FAST,
155 .rise_time_ns = 60,
156 .fall_time_ns = 60,
157 },
158 .i2c[2] = {
159 .speed = I2C_SPEED_FAST,
160 .rise_time_ns = 60,
161 .fall_time_ns = 60,
162 },
163 .i2c[3] = {
164 .speed = I2C_SPEED_FAST,
165 .rise_time_ns = 60,
166 .fall_time_ns = 60,
167 },
168 .i2c[4] = {
169 .speed = I2C_SPEED_FAST,
170 .rise_time_ns = 60,
171 .fall_time_ns = 60,
172 },
173 }"
174
175 # PCIe port 11 (x2) for NVMe hybrid storage devices
176 register "PcieRpEnable[10]" = "1"
177 register "PcieRpLtrEnable[10]" = "1"
178 # Uses CLK SRC 0
179 register "PcieClkSrcUsage[0]" = "6"
180 register "PcieClkSrcClkReq[0]" = "0"
181
182 # SATA port 1 Gen3 Strength
183 # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
184 register "sata_port[1].TxGen3DeEmphEnable" = "1"
185 register "sata_port[1].TxGen3DeEmph" = "0x20"
186
187 device domain 0 on
188 device ref dptf on
189 chip drivers/intel/dptf
190 ## Active Policy
191 register "policies.active[0]" = "{.target=DPTF_CPU,
192 .thresholds={TEMP_PCT(90, 0),}}"
193 register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
194 .thresholds={TEMP_PCT(75, 60),
195 TEMP_PCT(65, 50),
196 TEMP_PCT(45, 40),
197 TEMP_PCT(30, 30),}}"
198
199 ## Passive Policy
200 register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 85, 60000)"
201 register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 76, 60000)"
202
203 ## Critical Policy
204 register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 105, SHUTDOWN)"
205 register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
206
207 ## Power Limits Control
208 # 15-25W PL1 in 1000mW increments, avg over 28-32s interval
209 # 40-49W PL2 in 1000mW increments, avg over 28-32s interval
210 register "controls.power_limits.pl1" = "{
211 .min_power = 15000,
212 .max_power = 25000,
213 .time_window_min = 28 * MSECS_PER_SEC,
214 .time_window_max = 32 * MSECS_PER_SEC,
215 .granularity = 1000,}"
216 register "controls.power_limits.pl2" = "{
217 .min_power = 40000,
218 .max_power = 49000,
219 .time_window_min = 28 * MSECS_PER_SEC,
220 .time_window_max = 32 * MSECS_PER_SEC,
221 .granularity = 1000,}"
222
223 ## Fan Performance Control (Percent, Speed, Noise, Power)
224 register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }"
225 register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }"
226 register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }"
227 register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }"
228 register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }"
229 register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }"
230 register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }"
231 register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }"
232 register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }"
233 register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }"
234
235 # Fan options
236 register "options.fan.fine_grained_control" = "1"
237 register "options.fan.step_size" = "2"
238
239 device generic 0 on end
240 end
241 end
242 device ref xhci on
243 chip drivers/usb/acpi
244 device usb 0.0 on
245 chip drivers/usb/acpi
246 register "desc" = ""USB2 Type-A Port 0""
247 register "type" = "UPC_TYPE_A"
248 register "group" = "ACPI_PLD_GROUP(1, 1)"
249 device usb 2.0 on end
250 end
251 chip drivers/usb/acpi
252 register "desc" = ""USB2 Type-C Port 0""
253 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
254 register "group" = "ACPI_PLD_GROUP(2, 1)"
255 device usb 2.1 on end
256 end
257 chip drivers/usb/acpi
258 register "desc" = ""USB2 Type-A Port 1""
259 register "type" = "UPC_TYPE_A"
260 register "group" = "ACPI_PLD_GROUP(1, 2)"
261 device usb 2.2 on end
262 end
263 chip drivers/usb/acpi
264 device usb 2.3 off end
265 end
266 chip drivers/usb/acpi
267 register "desc" = ""USB2 Type-C Port 1""
268 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
269 register "group" = "ACPI_PLD_GROUP(2, 2)"
270 device usb 2.4 on end
271 end
272 chip drivers/usb/acpi
273 register "desc" = ""Camera""
274 register "type" = "UPC_TYPE_INTERNAL"
275 device usb 2.5 on end
276 end
277 chip drivers/usb/acpi
278 device usb 2.6 off end
279 end
280 chip drivers/usb/acpi
281 register "desc" = ""USB3 Type-A Port 0""
282 register "type" = "UPC_TYPE_USB3_A"
283 register "group" = "ACPI_PLD_GROUP(1, 1)"
284 device usb 3.0 on end
285 end
286 chip drivers/usb/acpi
287 register "desc" = ""USB3 Type-A Port 1""
288 register "type" = "UPC_TYPE_USB3_A"
289 register "group" = "ACPI_PLD_GROUP(1, 2)"
290 device usb 3.1 on end
291 end
292 chip drivers/usb/acpi
293 register "desc" = ""USB3 Type-C Port 1""
294 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
295 register "group" = "ACPI_PLD_GROUP(2, 2)"
296 device usb 3.2 on end
297 end
298 chip drivers/usb/acpi
299 register "desc" = ""USB3 Type-C Port 0""
300 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
301 register "group" = "ACPI_PLD_GROUP(2, 1)"
302 device usb 3.3 on end
303 end
304 chip drivers/usb/acpi
305 device usb 3.4 off end
306 end
307 chip drivers/usb/acpi
308 device usb 3.5 off end
309 end
310 end
311 end
312 end
313 device ref sdxc off end
314 device ref i2c0 on
315 # ALC1015
316 chip drivers/i2c/generic
317 register "hid" = ""10EC1015""
318 register "desc" = ""Realtek SPK AMP L""
319 register "uid" = "0"
320 device i2c 28 on end
321 end
322 chip drivers/i2c/generic
323 register "hid" = ""10EC1015""
324 register "desc" = ""Realtek SPK AMP R""
325 register "uid" = "1"
326 device i2c 29 on end
327 end
328 end
329 device ref i2c2 on end # LVDS
330 device ref i2c3 on
331 # Touchscreen
332 chip drivers/i2c/hid
333 register "generic.hid" = ""WDHT2002""
334 register "generic.desc" = ""WDT Touchscreen""
335 register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A20_IRQ)"
336 register "generic.probed" = "1"
337 register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D15)"
338 register "generic.reset_delay_ms" = "100"
339 register "generic.wake" = "GPE0_DW0_20"
340 register "generic.has_power_resource" = "1"
341 register "hid_desc_reg_offset" = "0x20"
342 device i2c 2c on end
343 end
344 end
345 device ref i2c4 on
346 chip drivers/i2c/generic
347 register "hid" = ""10EC5682""
348 register "name" = ""RT58""
349 register "desc" = ""Realtek RT5682""
350 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
351 register "property_count" = "1"
352 # Set the jd_src to RT5668_JD1 for jack detection
353 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
354 register "property_list[0].name" = ""realtek,jd-src""
355 register "property_list[0].integer" = "1"
356 device i2c 1a on
357 probe AUDIO_CODEC_SOURCE AUDIO_CODEC_UNPROVISIONED
358 probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682
359 end
360 end
361 chip drivers/i2c/generic
362 register "hid" = ""RTL5682""
363 register "name" = ""RT58""
364 register "desc" = ""Realtek RT5682""
365 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
366 register "property_count" = "1"
367 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
368 register "property_list[0].name" = ""realtek,jd-src""
369 register "property_list[0].integer" = "1"
370 device i2c 1a on
371 probe AUDIO_CODEC_SOURCE AUDIO_CODEC_ALC5682I_VS
372 end
373 end
374 chip drivers/generic/gpio_keys
375 register "name" = ""MUTE""
376 register "label" = ""mic_mute_switch""
377 register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_D16)"
378 register "key.wakeup_route" = "WAKEUP_ROUTE_DISABLED"
379 register "key.dev_name" = ""MMSW""
380 register "key.linux_code" = "SW_MUTE_DEVICE"
381 register "key.linux_input_type" = "EV_SW"
382 register "key.label" = ""mic_mute_switch_key""
383 device generic 0 on end
384 end
385 end
386 device ref emmc on end
387 device ref pcie_rp11 on
388 # X2 NVMe
389 register "PcieRpSlotImplemented[10]" = "1"
390 end
391 device ref hda on
392 chip drivers/sof
393 register "spkr_tplg" = "rt1015"
394 register "jack_tplg" = "rt5682"
395 register "mic_tplg" = "_2ch_pdm0"
396 device generic 0 on end
397 end
398 end
399 end
400
401 # VR Settings Configuration for 4 Domains
402 #+----------------+-------+-------+-------+-------+
403 #| Domain/Setting | SA | IA | GTUS | GTS |
404 #+----------------+-------+-------+-------+-------+
405 #| Psi1Threshold | 20A | 20A | 20A | 20A |
406 #| Psi2Threshold | 5A | 5A | 5A | 5A |
407 #| Psi3Threshold | 1A | 1A | 1A | 1A |
408 #| Psi3Enable | 1 | 1 | 1 | 1 |
409 #| Psi4Enable | 1 | 1 | 1 | 1 |
410 #| ImonSlope | 0 | 0 | 0 | 0 |
411 #| ImonOffset | 0 | 0 | 0 | 0 |
412 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
413 #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
414 #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
415 #+----------------+-------+-------+-------+-------+
416 #Note: IccMax settings are moved to SoC code
417 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
418 .vr_config_enable = 1,
419 .psi1threshold = VR_CFG_AMP(20),
420 .psi2threshold = VR_CFG_AMP(5),
421 .psi3threshold = VR_CFG_AMP(1),
422 .psi3enable = 1,
423 .psi4enable = 1,
424 .imon_slope = 0x0,
425 .imon_offset = 0x0,
426 .icc_max = 0,
427 .voltage_limit = 1520,
428 .ac_loadline = 1004,
429 .dc_loadline = 1004,
430 }"
431
432 register "domain_vr_config[VR_IA_CORE]" = "{
433 .vr_config_enable = 1,
434 .psi1threshold = VR_CFG_AMP(20),
435 .psi2threshold = VR_CFG_AMP(5),
436 .psi3threshold = VR_CFG_AMP(1),
437 .psi3enable = 1,
438 .psi4enable = 1,
439 .imon_slope = 0x0,
440 .imon_offset = 0x0,
441 .icc_max = 0,
442 .voltage_limit = 1520,
443 .ac_loadline = 181,
444 .dc_loadline = 181,
445 }"
446
447 register "domain_vr_config[VR_GT_UNSLICED]" = "{
448 .vr_config_enable = 1,
449 .psi1threshold = VR_CFG_AMP(20),
450 .psi2threshold = VR_CFG_AMP(5),
451 .psi3threshold = VR_CFG_AMP(1),
452 .psi3enable = 1,
453 .psi4enable = 1,
454 .imon_slope = 0x0,
455 .imon_offset = 0x0,
456 .icc_max = 0,
457 .voltage_limit = 1520,
458 .ac_loadline = 319,
459 .dc_loadline = 319,
460 }"
461
462 register "domain_vr_config[VR_GT_SLICED]" = "{
463 .vr_config_enable = 1,
464 .psi1threshold = VR_CFG_AMP(20),
465 .psi2threshold = VR_CFG_AMP(5),
466 .psi3threshold = VR_CFG_AMP(1),
467 .psi3enable = 1,
468 .psi4enable = 1,
469 .imon_slope = 0x0,
470 .imon_offset = 0x0,
471 .icc_max = 0,
472 .voltage_limit = 1520,
473 .ac_loadline = 319,
474 .dc_loadline = 319,
475 }"
476
477 end
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