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mainboard/intel/avenuecity_crb: Update full IIO configuration
[coreboot2.git] / src / mainboard / google / puff / variants / duffy / overridetree.cb
blob38752d27906c49a393be3e73cf6b26976e93c400
1 chip soc/intel/cannonlake
2 register "tcc_offset" = "5" # TCC of 95C
3
4 register "power_limits_config" = "{
5 .tdp_pl1_override = 15,
6 .tdp_pl2_override = 51,
7 }"
8
9 # Auto-switch between X4 NVMe and X2 NVMe.
10 register "TetonGlacierMode" = "1"
11
12 register "SerialIoDevMode" = "{
13 [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
14 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
15 [PchSerialIoIndexI2C2] = PchSerialIoPci,
16 [PchSerialIoIndexI2C3] = PchSerialIoPci,
17 [PchSerialIoIndexI2C4] = PchSerialIoPci,
18 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
19 [PchSerialIoIndexSPI0] = PchSerialIoPci,
20 [PchSerialIoIndexSPI1] = PchSerialIoDisabled,
21 [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
22 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
23 [PchSerialIoIndexUART1] = PchSerialIoDisabled,
24 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
25 }"
26
27 # USB configuration
28 register "usb2_ports[0]" = "{
29 .enable = 1,
30 .ocpin = OC2,
31 .tx_bias = USB2_BIAS_0MV,
32 .tx_emp_enable = USB2_PRE_EMP_ON,
33 .pre_emp_bias = USB2_BIAS_11P25MV,
34 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
35 }" # Type-A Port 2
36 register "usb2_ports[1]" = "{
37 .enable = 1,
38 .ocpin = OC1,
39 .tx_bias = USB2_BIAS_0MV,
40 .tx_emp_enable = USB2_PRE_EMP_ON,
41 .pre_emp_bias = USB2_BIAS_28P15MV,
42 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
43 }" # Type-A Port 1
44 register "usb2_ports[2]" = "{
45 .enable = 1,
46 .ocpin = OC3,
47 .tx_bias = USB2_BIAS_0MV,
48 .tx_emp_enable = USB2_PRE_EMP_ON,
49 .pre_emp_bias = USB2_BIAS_28P15MV,
50 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
51 }" # Type-A Port 3
52 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
53 register "usb2_ports[4]" = "{
54 .enable = 1,
55 .ocpin = OC_SKIP,
56 .tx_bias = USB2_BIAS_0MV,
57 .tx_emp_enable = USB2_PRE_EMP_ON,
58 .pre_emp_bias = USB2_BIAS_28P15MV,
59 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
60 }" # Type-A Port 4
61 register "usb2_ports[5]" = "{
62 .enable = 1,
63 .ocpin = OC0,
64 .tx_bias = USB2_BIAS_0MV,
65 .tx_emp_enable = USB2_PRE_EMP_ON,
66 .pre_emp_bias = USB2_BIAS_28P15MV,
67 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
68 }" # Type-A port 0
69 register "usb2_ports[9]" = "{
70 .enable = 1,
71 .ocpin = OC_SKIP,
72 .tx_bias = USB2_BIAS_0MV,
73 .tx_emp_enable = USB2_PRE_EMP_ON,
74 .pre_emp_bias = USB2_BIAS_28P15MV,
75 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
76 }" # BT
77
78 register "usb3_ports[0]" = "{
79 .enable = 1,
80 .ocpin = OC2,
81 .tx_de_emp = 0x00,
82 .tx_downscale_amp = 0x00,
83 .gen2_tx_rate0_uniq_tran_enable = 0,
84 .gen2_tx_rate0_uniq_tran = 0x00,
85 .gen2_tx_rate1_uniq_tran_enable = 0,
86 .gen2_tx_rate1_uniq_tran = 0x00,
87 .gen2_tx_rate2_uniq_tran_enable = 1,
88 .gen2_tx_rate2_uniq_tran = 0x4c,
89 .gen2_tx_rate3_uniq_tran_enable = 0,
90 .gen2_tx_rate3_uniq_tran = 0x00,
91 .gen2_rx_tuning_enable = 0x0f,
92 .gen2_rx_tuning_params = 0x45,
93 .gen2_rx_filter_sel = 0x44,
94 }" # Type-A Port 2
95 register "usb3_ports[1]" = "USB3_PORT_GEN2_DEFAULT(OC3)" # Type-A Port 3
96 register "usb3_ports[2]" = "{
97 .enable = 1,
98 .ocpin = OC1,
99 .tx_de_emp = 0x00,
100 .tx_downscale_amp = 0x00,
101 .gen2_tx_rate0_uniq_tran_enable = 0,
102 .gen2_tx_rate0_uniq_tran = 0x00,
103 .gen2_tx_rate1_uniq_tran_enable = 0,
104 .gen2_tx_rate1_uniq_tran = 0x00,
105 .gen2_tx_rate2_uniq_tran_enable = 1,
106 .gen2_tx_rate2_uniq_tran = 0x4c,
107 .gen2_tx_rate3_uniq_tran_enable = 0,
108 .gen2_tx_rate3_uniq_tran = 0x00,
109 .gen2_rx_tuning_enable = 0x0f,
110 .gen2_rx_tuning_params = 0x3d,
111 .gen2_rx_filter_sel = 0x44,
112 }" # Type-A Port 1
113 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
114 register "usb3_ports[4]" = "{
115 .enable = 1,
116 .ocpin = OC0,
117 .tx_de_emp = 0x00,
118 .tx_downscale_amp = 0x00,
119 .gen2_tx_rate0_uniq_tran_enable = 0,
120 .gen2_tx_rate0_uniq_tran = 0x00,
121 .gen2_tx_rate1_uniq_tran_enable = 0,
122 .gen2_tx_rate1_uniq_tran = 0x00,
123 .gen2_tx_rate2_uniq_tran_enable = 1,
124 .gen2_tx_rate2_uniq_tran = 0x4c,
125 .gen2_tx_rate3_uniq_tran_enable = 0,
126 .gen2_tx_rate3_uniq_tran = 0x00,
127 .gen2_rx_tuning_enable = 0x0f,
128 .gen2_rx_tuning_params = 0x45,
129 .gen2_rx_filter_sel = 0x44,
130 }" # Type-A Port 0
131 register "usb3_ports[5]" = "{
132 .enable = 1,
133 .ocpin = OC_SKIP,
134 .tx_de_emp = 0x00,
135 .tx_downscale_amp = 0x00,
136 .gen2_tx_rate0_uniq_tran_enable = 0,
137 .gen2_tx_rate0_uniq_tran = 0x00,
138 .gen2_tx_rate1_uniq_tran_enable = 0,
139 .gen2_tx_rate1_uniq_tran = 0x00,
140 .gen2_tx_rate2_uniq_tran_enable = 1,
141 .gen2_tx_rate2_uniq_tran = 0x4c,
142 .gen2_tx_rate3_uniq_tran_enable = 0,
143 .gen2_tx_rate3_uniq_tran = 0x00,
144 .gen2_rx_tuning_enable = 0x0f,
145 .gen2_rx_tuning_params = 0x45,
146 .gen2_rx_filter_sel = 0x44,
147 }" # Type-A Port 4
148
149 # Bitmap for Wake Enable on USB attach/detach
150 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
151 USB_PORT_WAKE_ENABLE(2) |
152 USB_PORT_WAKE_ENABLE(3) |
153 USB_PORT_WAKE_ENABLE(5) |
154 USB_PORT_WAKE_ENABLE(6)"
155 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
156 USB_PORT_WAKE_ENABLE(2) |
157 USB_PORT_WAKE_ENABLE(3) |
158 USB_PORT_WAKE_ENABLE(5) |
159 USB_PORT_WAKE_ENABLE(6)"
160
161 # Enable eMMC HS400
162 register "ScsEmmcHs400Enabled" = "1"
163
164 # EMMC Tx CMD Delay
165 # Refer to EDS-Vol2-14.3.7.
166 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
167 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
168 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
169
170 # EMMC TX DATA Delay 1
171 # Refer to EDS-Vol2-14.3.8.
172 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
173 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
174 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
175
176 # EMMC TX DATA Delay 2
177 # Refer to EDS-Vol2-14.3.9.
178 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
179 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
180 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
181 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
182 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
183
184 # EMMC RX CMD/DATA Delay 1
185 # Refer to EDS-Vol2-14.3.10.
186 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
187 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
188 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
189 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
190 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
191
192 # EMMC RX CMD/DATA Delay 2
193 # Refer to EDS-Vol2-14.3.12.
194 # [17:16] stands for Rx Clock before Output Buffer,
195 # 00: Rx clock after output buffer,
196 # 01: Rx clock before output buffer,
197 # 10: Automatic selection based on working mode.
198 # 11: Reserved
199 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
200 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
201 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
202
203 # EMMC Rx Strobe Delay
204 # Refer to EDS-Vol2-14.3.11.
205 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
206 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
207 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
208
209 # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them.
210 register "PchHdaAudioLinkSsp1" = "0"
211 register "PchHdaAudioLinkDmic0" = "0"
212
213 # Intel Common SoC Config
214 #+-------------------+---------------------------+
215 #| Field | Value |
216 #+-------------------+---------------------------+
217 #| GSPI0 | cr50 TPM. Early init is |
218 #| | required to set up a BAR |
219 #| | for TPM communication |
220 #| | before memory is up |
221 #| I2C2 | PS175 |
222 #| I2C3 | MST |
223 #| I2C4 | Audio |
224 #+-------------------+---------------------------+
225 register "common_soc_config" = "{
226 .gspi[0] = {
227 .speed_mhz = 1,
228 .early_init = 1,
229 },
230 .i2c[2] = {
231 .speed = I2C_SPEED_FAST,
232 .rise_time_ns = 60,
233 .fall_time_ns = 60,
234 },
235 .i2c[3] = {
236 .speed = I2C_SPEED_FAST,
237 .rise_time_ns = 60,
238 .fall_time_ns = 60,
239 },
240 .i2c[4] = {
241 .speed = I2C_SPEED_FAST,
242 .rise_time_ns = 60,
243 .fall_time_ns = 60,
244 },
245 }"
246
247 # PCIe port 7 for LAN
248 register "PcieRpEnable[6]" = "1"
249 register "PcieRpLtrEnable[6]" = "1"
250 # PCIe port 11 (x2) for NVMe hybrid storage devices
251 register "PcieRpEnable[10]" = "1"
252 register "PcieRpLtrEnable[10]" = "1"
253 # Uses CLK SRC 0
254 register "PcieClkSrcUsage[0]" = "6"
255 register "PcieClkSrcClkReq[0]" = "0"
256
257 # GPIO for SD card detect
258 register "sdcard_cd_gpio" = "vSD3_CD_B"
259
260 # SATA port 1 Gen3 Strength
261 # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
262 register "sata_port[1].TxGen3DeEmphEnable" = "1"
263 register "sata_port[1].TxGen3DeEmph" = "0x20"
264
265 device domain 0 on
266 device ref dptf on
267 chip drivers/intel/dptf
268 ## Active Policy
269 register "policies.active[0]" = "{.target=DPTF_CPU,
270 .thresholds={TEMP_PCT(94, 0),}}"
271 register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
272 .thresholds={TEMP_PCT(65, 90),
273 TEMP_PCT(61, 80),
274 TEMP_PCT(57, 70),
275 TEMP_PCT(53, 60),
276 TEMP_PCT(49, 50),
277 TEMP_PCT(45, 40),
278 TEMP_PCT(41, 0),}}"
279
280 ## Passive Policy
281 register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
282 register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 68, 5000)"
283
284 ## Critical Policy
285 register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
286 register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 78, SHUTDOWN)"
287
288 ## Power Limits Control
289 # PL1 is fixed at 15W, avg over 28-32s interval
290 # 15-51W PL2 in 1000mW increments, avg over 28-32s interval
291 register "controls.power_limits.pl1" = "{
292 .min_power = 15000,
293 .max_power = 15000,
294 .time_window_min = 28 * MSECS_PER_SEC,
295 .time_window_max = 32 * MSECS_PER_SEC,
296 .granularity = 200,}"
297 register "controls.power_limits.pl2" = "{
298 .min_power = 15000,
299 .max_power = 51000,
300 .time_window_min = 28 * MSECS_PER_SEC,
301 .time_window_max = 32 * MSECS_PER_SEC,
302 .granularity = 1000,}"
303
304 ## Charger Performance Control (Control, mA)
305 register "controls.charger_perf[0]" = "{ 255, 1700 }"
306 register "controls.charger_perf[1]" = "{ 24, 1500 }"
307 register "controls.charger_perf[2]" = "{ 16, 1000 }"
308 register "controls.charger_perf[3]" = "{ 8, 500 }"
309
310 ## Fan Performance Control (Percent, Speed, Noise, Power)
311 register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }"
312 register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }"
313 register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }"
314 register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }"
315 register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }"
316 register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }"
317 register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }"
318 register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }"
319 register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }"
320 register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }"
321
322 # Fan options
323 register "options.fan.fine_grained_control" = "1"
324 register "options.fan.step_size" = "2"
325
326 device generic 0 on end
327 end
328 end
329 device ref xhci on
330 chip drivers/usb/acpi
331 device usb 0.0 on
332 chip drivers/usb/acpi
333 register "desc" = ""USB2 Type-A Front Left""
334 register "type" = "UPC_TYPE_A"
335 register "group" = "ACPI_PLD_GROUP(0, 0)"
336 device usb 2.0 on end
337 end
338 chip drivers/usb/acpi
339 register "desc" = ""USB2 Type-C Port Rear""
340 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
341 register "group" = "ACPI_PLD_GROUP(1, 3)"
342 device usb 2.1 on end
343 end
344 chip drivers/usb/acpi
345 register "desc" = ""USB2 Type-A Front Right""
346 register "type" = "UPC_TYPE_A"
347 register "group" = "ACPI_PLD_GROUP(0, 1)"
348 device usb 2.2 on end
349 end
350 chip drivers/usb/acpi
351 register "desc" = ""USB2 Type-A Rear Right""
352 register "type" = "UPC_TYPE_A"
353 register "group" = "ACPI_PLD_GROUP(1, 2)"
354 device usb 2.3 on end
355 end
356 chip drivers/usb/acpi
357 register "desc" = ""USB2 Type-A Rear Middle""
358 register "type" = "UPC_TYPE_A"
359 register "group" = "ACPI_PLD_GROUP(1, 1)"
360 device usb 2.4 on end
361 end
362 chip drivers/usb/acpi
363 register "desc" = ""USB2 Type-A Rear Left""
364 register "type" = "UPC_TYPE_A"
365 register "group" = "ACPI_PLD_GROUP(1, 0)"
366 device usb 2.5 on end
367 end
368 chip drivers/usb/acpi
369 device usb 2.6 off end
370 end
371 chip drivers/usb/acpi
372 register "desc" = ""USB3 Type-A Front Left""
373 register "type" = "UPC_TYPE_USB3_A"
374 register "group" = "ACPI_PLD_GROUP(0, 0)"
375 device usb 3.0 on end
376 end
377 chip drivers/usb/acpi
378 register "desc" = ""USB3 Type-A Front Right""
379 register "type" = "UPC_TYPE_USB3_A"
380 register "group" = "ACPI_PLD_GROUP(0, 1)"
381 device usb 3.1 on end
382 end
383 chip drivers/usb/acpi
384 register "desc" = ""USB3 Type-A Rear Right""
385 register "type" = "UPC_TYPE_USB3_A"
386 register "group" = "ACPI_PLD_GROUP(1, 2)"
387 device usb 3.2 on end
388 end
389 chip drivers/usb/acpi
390 register "desc" = ""USB3 Type-C Rear""
391 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
392 register "group" = "ACPI_PLD_GROUP(1, 3)"
393 device usb 3.3 on end
394 end
395 chip drivers/usb/acpi
396 register "desc" = ""USB3 Type-A Rear Left""
397 register "type" = "UPC_TYPE_USB3_A"
398 register "group" = "ACPI_PLD_GROUP(1, 0)"
399 device usb 3.4 on end
400 end
401 chip drivers/usb/acpi
402 register "desc" = ""USB3 Type-A Rear Middle""
403 register "type" = "UPC_TYPE_USB3_A"
404 register "group" = "ACPI_PLD_GROUP(1, 1)"
405 device usb 3.5 on end
406 end
407 end
408 end
409 end
410 device ref i2c2 on
411 # PCON PS175
412 chip drivers/i2c/generic
413 register "hid" = ""1AF80175""
414 register "name" = ""PS17""
415 register "desc" = ""Parade PS175""
416 device i2c 4a hidden end
417 end
418 end
419 device ref i2c3 on
420 # Realtek RTD2142
421 chip drivers/i2c/generic
422 register "hid" = ""10EC2142""
423 register "name" = ""RTD2""
424 register "desc" = ""Realtek RTD2142""
425 device i2c 4a hidden end
426 end
427 end
428 device ref i2c4 on
429 chip drivers/i2c/generic
430 register "hid" = ""10EC5682""
431 register "name" = ""RT58""
432 register "desc" = ""Realtek RT5682""
433 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
434 register "property_count" = "1"
435 # Set the jd_src to RT5668_JD1 for jack detection
436 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
437 register "property_list[0].name" = ""realtek,jd-src""
438 register "property_list[0].integer" = "1"
439 device i2c 1a on end
440 end
441 end
442 device ref emmc on end
443 device ref pcie_rp7 on
444 # RTL8111H Ethernet NIC
445 chip drivers/net
446 register "customized_leds" = "0x05af"
447 register "wake" = "GPE0_DW1_07" # GPP_C7
448 register "device_index" = "0"
449 register "enable_aspm_l1_2" = "1"
450 device pci 00.0 on end
451 end
452 register "PcieRpSlotImplemented[6]" = "1"
453 end
454 device ref pcie_rp11 on
455 # X2 NVMe
456 register "PcieRpSlotImplemented[10]" = "1"
457 end
458 end
459
460 # VR Settings Configuration for 4 Domains
461 #+----------------+-------+-------+-------+-------+
462 #| Domain/Setting | SA | IA | GTUS | GTS |
463 #+----------------+-------+-------+-------+-------+
464 #| Psi1Threshold | 20A | 20A | 20A | 20A |
465 #| Psi2Threshold | 5A | 5A | 5A | 5A |
466 #| Psi3Threshold | 1A | 1A | 1A | 1A |
467 #| Psi3Enable | 1 | 1 | 1 | 1 |
468 #| Psi4Enable | 1 | 1 | 1 | 1 |
469 #| ImonSlope | 0 | 0 | 0 | 0 |
470 #| ImonOffset | 0 | 0 | 0 | 0 |
471 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
472 #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
473 #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
474 #+----------------+-------+-------+-------+-------+
475 #Note: IccMax settings are moved to SoC code
476 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
477 .vr_config_enable = 1,
478 .psi1threshold = VR_CFG_AMP(20),
479 .psi2threshold = VR_CFG_AMP(5),
480 .psi3threshold = VR_CFG_AMP(1),
481 .psi3enable = 1,
482 .psi4enable = 1,
483 .imon_slope = 0x0,
484 .imon_offset = 0x0,
485 .icc_max = 0,
486 .voltage_limit = 1520,
487 .ac_loadline = 1004,
488 .dc_loadline = 1004,
489 }"
490
491 register "domain_vr_config[VR_IA_CORE]" = "{
492 .vr_config_enable = 1,
493 .psi1threshold = VR_CFG_AMP(20),
494 .psi2threshold = VR_CFG_AMP(5),
495 .psi3threshold = VR_CFG_AMP(1),
496 .psi3enable = 1,
497 .psi4enable = 1,
498 .imon_slope = 0x0,
499 .imon_offset = 0x0,
500 .icc_max = 0,
501 .voltage_limit = 1520,
502 .ac_loadline = 181,
503 .dc_loadline = 181,
504 }"
505
506 register "domain_vr_config[VR_GT_UNSLICED]" = "{
507 .vr_config_enable = 1,
508 .psi1threshold = VR_CFG_AMP(20),
509 .psi2threshold = VR_CFG_AMP(5),
510 .psi3threshold = VR_CFG_AMP(1),
511 .psi3enable = 1,
512 .psi4enable = 1,
513 .imon_slope = 0x0,
514 .imon_offset = 0x0,
515 .icc_max = 0,
516 .voltage_limit = 1520,
517 .ac_loadline = 319,
518 .dc_loadline = 319,
519 }"
520
521 register "domain_vr_config[VR_GT_SLICED]" = "{
522 .vr_config_enable = 1,
523 .psi1threshold = VR_CFG_AMP(20),
524 .psi2threshold = VR_CFG_AMP(5),
525 .psi3threshold = VR_CFG_AMP(1),
526 .psi3enable = 1,
527 .psi4enable = 1,
528 .imon_slope = 0x0,
529 .imon_offset = 0x0,
530 .icc_max = 0,
531 .voltage_limit = 1520,
532 .ac_loadline = 319,
533 .dc_loadline = 319,
534 }"
535
536 end
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