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mainboard/intel/avenuecity_crb: Update full IIO configuration
[coreboot2.git] / src / mainboard / google / puff / variants / moonbuggy / overridetree.cb
blob95f6965e403b0b819bd9ece622fbac439439d463
1 chip soc/intel/cannonlake
2 # Auto-switch between X4 NVMe and X2 NVMe.
3 register "TetonGlacierMode" = "1"
4
5 register "SerialIoDevMode" = "{
6 [PchSerialIoIndexI2C0] = PchSerialIoDisabled,
7 [PchSerialIoIndexI2C1] = PchSerialIoDisabled,
8 [PchSerialIoIndexI2C2] = PchSerialIoPci,
9 [PchSerialIoIndexI2C3] = PchSerialIoPci,
10 [PchSerialIoIndexI2C4] = PchSerialIoPci,
11 [PchSerialIoIndexI2C5] = PchSerialIoDisabled,
12 [PchSerialIoIndexSPI0] = PchSerialIoPci,
13 [PchSerialIoIndexSPI1] = PchSerialIoDisabled,
14 [PchSerialIoIndexSPI2] = PchSerialIoDisabled,
15 [PchSerialIoIndexUART0] = PchSerialIoSkipInit,
16 [PchSerialIoIndexUART1] = PchSerialIoPci,
17 [PchSerialIoIndexUART2] = PchSerialIoDisabled,
18 }"
19
20 # USB configuration
21 register "usb2_ports[0]" = "{
22 .enable = 1,
23 .ocpin = OC2,
24 .tx_bias = USB2_BIAS_0MV,
25 .tx_emp_enable = USB2_PRE_EMP_ON,
26 .pre_emp_bias = USB2_BIAS_11P25MV,
27 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
28 }" # Type-A Port 2
29 register "usb2_ports[1]" = "{
30 .enable = 1,
31 .ocpin = OC1,
32 .tx_bias = USB2_BIAS_0MV,
33 .tx_emp_enable = USB2_PRE_EMP_ON,
34 .pre_emp_bias = USB2_BIAS_28P15MV,
35 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
36 }" # Type-A Port 1
37 register "usb2_ports[2]" = "{
38 .enable = 1,
39 .ocpin = OC3,
40 .tx_bias = USB2_BIAS_0MV,
41 .tx_emp_enable = USB2_PRE_EMP_ON,
42 .pre_emp_bias = USB2_BIAS_28P15MV,
43 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
44 }" # Type-A Port 3
45 register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port
46 register "usb2_ports[4]" = "{
47 .enable = 1,
48 .ocpin = OC_SKIP,
49 .tx_bias = USB2_BIAS_0MV,
50 .tx_emp_enable = USB2_PRE_EMP_ON,
51 .pre_emp_bias = USB2_BIAS_28P15MV,
52 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
53 }" # Type-A Port 4
54 register "usb2_ports[5]" = "{
55 .enable = 1,
56 .ocpin = OC0,
57 .tx_bias = USB2_BIAS_0MV,
58 .tx_emp_enable = USB2_PRE_EMP_ON,
59 .pre_emp_bias = USB2_BIAS_28P15MV,
60 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
61 }" # Type-A port 0
62 register "usb2_ports[6]" = "USB2_PORT_EMPTY"
63 register "usb2_ports[7]" = "USB2_PORT_EMPTY"
64 register "usb2_ports[8]" = "USB2_PORT_EMPTY"
65 register "usb2_ports[9]" = "{
66 .enable = 1,
67 .ocpin = OC_SKIP,
68 .tx_bias = USB2_BIAS_0MV,
69 .tx_emp_enable = USB2_PRE_EMP_ON,
70 .pre_emp_bias = USB2_BIAS_28P15MV,
71 .pre_emp_bit = USB2_HALF_BIT_PRE_EMP,
72 }" # BT
73
74 register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-A Port 2
75 register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-A Port 3
76 register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC1)" # Type-A Port 1
77 register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C
78 register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port 0
79 register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Port 4
80
81 # Bitmap for Wake Enable on USB attach/detach
82 register "usb2_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
83 USB_PORT_WAKE_ENABLE(2) |
84 USB_PORT_WAKE_ENABLE(3) |
85 USB_PORT_WAKE_ENABLE(5) |
86 USB_PORT_WAKE_ENABLE(6)"
87 register "usb3_wake_enable_bitmap" = "USB_PORT_WAKE_ENABLE(1) |
88 USB_PORT_WAKE_ENABLE(2) |
89 USB_PORT_WAKE_ENABLE(3) |
90 USB_PORT_WAKE_ENABLE(5) |
91 USB_PORT_WAKE_ENABLE(6)"
92
93 # Enable eMMC HS400
94 register "ScsEmmcHs400Enabled" = "1"
95
96 # EMMC Tx CMD Delay
97 # Refer to EDS-Vol2-14.3.7.
98 # [14:8] steps of delay for DDR mode, each 125ps, range: 0 - 39.
99 # [6:0] steps of delay for SDR mode, each 125ps, range: 0 - 39.
100 register "common_soc_config.emmc_dll.emmc_tx_cmd_cntl" = "0x505"
101
102 # EMMC TX DATA Delay 1
103 # Refer to EDS-Vol2-14.3.8.
104 # [14:8] steps of delay for HS400, each 125ps, range: 0 - 78.
105 # [6:0] steps of delay for SDR104/HS200, each 125ps, range: 0 - 79.
106 register "common_soc_config.emmc_dll.emmc_tx_data_cntl1" = "0x911"
107
108 # EMMC TX DATA Delay 2
109 # Refer to EDS-Vol2-14.3.9.
110 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 79.
111 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
112 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 -79.
113 # [6:0] steps of delay for SDR12, each 125ps. Range: 0 - 79.
114 register "common_soc_config.emmc_dll.emmc_tx_data_cntl2" = "0x1C262828"
115
116 # EMMC RX CMD/DATA Delay 1
117 # Refer to EDS-Vol2-14.3.10.
118 # [30:24] steps of delay for SDR50, each 125ps, range: 0 - 119.
119 # [22:16] steps of delay for DDR50, each 125ps, range: 0 - 78.
120 # [14:8] steps of delay for SDR25/HS50, each 125ps, range: 0 - 119.
121 # [6:0] steps of delay for SDR12, each 125ps, range: 0 - 119.
122 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl1" = "0x1C16583b"
123
124 # EMMC RX CMD/DATA Delay 2
125 # Refer to EDS-Vol2-14.3.12.
126 # [17:16] stands for Rx Clock before Output Buffer,
127 # 00: Rx clock after output buffer,
128 # 01: Rx clock before output buffer,
129 # 10: Automatic selection based on working mode.
130 # 11: Reserved
131 # [14:8] steps of delay for Auto Tuning Mode, each 125ps, range: 0 - 39.
132 # [6:0] steps of delay for HS200, each 125ps, range: 0 - 79.
133 register "common_soc_config.emmc_dll.emmc_rx_cmd_data_cntl2" = "0x1001D"
134
135 # EMMC Rx Strobe Delay
136 # Refer to EDS-Vol2-14.3.11.
137 # [14:8] Rx Strobe Delay DLL 1(HS400 Mode), each 125ps, range: 0 - 39.
138 # [6:0] Rx Strobe Delay DLL 2(HS400 Mode), each 125ps, range: 0 - 39.
139 register "common_soc_config.emmc_dll.emmc_rx_strobe_cntl" = "0x1515"
140
141 # Intel HDA - disable I2S Audio SSP1 and DMIC0 as puff variant does not have them.
142 register "PchHdaAudioLinkSsp1" = "0"
143 register "PchHdaAudioLinkDmic0" = "0"
144
145 # Intel Common SoC Config
146 #+-------------------+---------------------------+
147 #| Field | Value |
148 #+-------------------+---------------------------+
149 #| GSPI0 | cr50 TPM. Early init is |
150 #| | required to set up a BAR |
151 #| | for TPM communication |
152 #| | before memory is up |
153 #| I2C2 | PS175 |
154 #| I2C3 | MST |
155 #| I2C4 | Audio |
156 #+-------------------+---------------------------+
157 register "common_soc_config" = "{
158 .gspi[0] = {
159 .speed_mhz = 1,
160 .early_init = 1,
161 },
162 .i2c[2] = {
163 .speed = I2C_SPEED_FAST,
164 .rise_time_ns = 60,
165 .fall_time_ns = 60,
166 },
167 .i2c[3] = {
168 .speed = I2C_SPEED_FAST,
169 .rise_time_ns = 60,
170 .fall_time_ns = 60,
171 },
172 .i2c[4] = {
173 .speed = I2C_SPEED_FAST,
174 .rise_time_ns = 60,
175 .fall_time_ns = 60,
176 },
177 }"
178
179 # PCIe root port 7 for LAN
180 register "PcieRpEnable[6]" = "1"
181 register "PcieRpLtrEnable[6]" = "1"
182 # Uses CLK SRC 0
183 register "PcieClkSrcUsage[0]" = "6"
184 register "PcieClkSrcClkReq[0]" = "0"
185
186 # PCIe root port 8 for WLAN
187 register "PcieRpEnable[7]" = "1"
188 register "PcieRpLtrEnable[7]" = "1"
189 # Uses CLK SRC 5
190 register "PcieClkSrcUsage[5]" = "7"
191 register "PcieClkSrcClkReq[5]" = "5"
192
193 # PCIe root port 9 for SSD (PCIe Lanes 11, 12)
194 register "PcieRpEnable[8]" = "1"
195 register "PcieRpLtrEnable[8]" = "1"
196 # RP 9 uses CLK SRC 1
197 register "PcieClkSrcUsage[1]" = "8"
198 register "PcieClkSrcClkReq[1]" = "1"
199
200 # PCIe root port 10 disabled
201 register "PcieRpEnable[9]" = "0"
202
203 # PCIe root port 11 TPU1
204 register "PcieRpEnable[10]" = "1"
205 register "PcieRpLtrEnable[10]" = "1"
206 # RP 11 uses CLK SRC 1
207 register "PcieClkSrcUsage[4]" = "10"
208 register "PcieClkSrcClkReq[4]" = "4"
209
210 # PCIe root port 12 TPU0
211 register "PcieRpEnable[11]" = "1"
212 register "PcieRpLtrEnable[11]" = "1"
213 # RP 11 uses CLK SRC 1
214 register "PcieClkSrcUsage[2]" = "11"
215 register "PcieClkSrcClkReq[2]" = "2"
216
217 # PCIe port 13 for i350 NIC (x4)
218 register "PcieRpEnable[12]" = "1"
219 register "PcieRpLtrEnable[12]" = "1"
220 # RP 13 uses CLK SRC 3
221 register "PcieClkSrcUsage[3]" = "12"
222 # RP 13 does not use a source clock request line
223 # NOTE: Any value other than a valid source-clock-request (0-5) is
224 # effectively "not connected"
225 register "PcieClkSrcClkReq[3]" = "0xFF"
226 # Disable the remaining ports 14-16
227 register "PcieRpEnable[13]" = "0"
228 register "PcieRpEnable[14]" = "0"
229 register "PcieRpEnable[15]" = "0"
230
231 # GPIO for SD card detect
232 register "sdcard_cd_gpio" = "vSD3_CD_B"
233
234 # SATA port 1 Gen3 Strength
235 # Port1 Tx De-Emphasis = 20*log(0x20/64) = -6dB
236 register "sata_port[1].TxGen3DeEmphEnable" = "1"
237 register "sata_port[1].TxGen3DeEmph" = "0x20"
238
239 device domain 0 on
240 device ref dptf on
241 chip drivers/intel/dptf
242 ## Active Policy
243 register "policies.active[0]" = "{.target=DPTF_CPU,
244 .thresholds={TEMP_PCT(94, 0),}}"
245 register "policies.active[1]" = "{.target=DPTF_TEMP_SENSOR_0,
246 .thresholds={TEMP_PCT(72, 90),
247 TEMP_PCT(68, 80),
248 TEMP_PCT(62, 70),
249 TEMP_PCT(54, 60),
250 TEMP_PCT(46, 50),
251 TEMP_PCT(39, 40),}}"
252
253 ## Passive Policy
254 register "policies.passive[0]" = "DPTF_PASSIVE(CPU, CPU, 95, 5000)"
255 register "policies.passive[1]" = "DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 6000)"
256
257 ## Critical Policy
258 register "policies.critical[0]" = "DPTF_CRITICAL(CPU, 100, SHUTDOWN)"
259 register "policies.critical[1]" = "DPTF_CRITICAL(TEMP_SENSOR_0, 90, SHUTDOWN)"
260
261 ## Power Limits Control
262 # PL1 is fixed at 15W, avg over 28-32s interval
263 # 51-51W PL2 in 1000mW increments, avg over 28-32s interval
264 register "controls.power_limits.pl1" = "{
265 .min_power = 15000,
266 .max_power = 15000,
267 .time_window_min = 28 * MSECS_PER_SEC,
268 .time_window_max = 32 * MSECS_PER_SEC,
269 .granularity = 125,}"
270 register "controls.power_limits.pl2" = "{
271 .min_power = 51000,
272 .max_power = 51000,
273 .time_window_min = 28 * MSECS_PER_SEC,
274 .time_window_max = 32 * MSECS_PER_SEC,
275 .granularity = 1000,}"
276
277 ## Charger Performance Control (Control, mA)
278 register "controls.charger_perf[0]" = "{ 255, 1700 }"
279 register "controls.charger_perf[1]" = "{ 24, 1500 }"
280 register "controls.charger_perf[2]" = "{ 16, 1000 }"
281 register "controls.charger_perf[3]" = "{ 8, 500 }"
282
283 ## Fan Performance Control (Percent, Speed, Noise, Power)
284 register "controls.fan_perf[0]" = "{ 90, 6700, 220, 2200, }"
285 register "controls.fan_perf[1]" = "{ 80, 5800, 180, 1800, }"
286 register "controls.fan_perf[2]" = "{ 70, 5000, 145, 1450, }"
287 register "controls.fan_perf[3]" = "{ 60, 4900, 115, 1150, }"
288 register "controls.fan_perf[4]" = "{ 50, 3838, 90, 900, }"
289 register "controls.fan_perf[5]" = "{ 40, 2904, 55, 550, }"
290 register "controls.fan_perf[6]" = "{ 30, 2337, 30, 300, }"
291 register "controls.fan_perf[7]" = "{ 20, 1608, 15, 150, }"
292 register "controls.fan_perf[8]" = "{ 10, 800, 10, 100, }"
293 register "controls.fan_perf[9]" = "{ 0, 0, 0, 50, }"
294
295 # Fan options
296 register "options.fan.fine_grained_control" = "1"
297 register "options.fan.step_size" = "2"
298
299 device generic 0 on end
300 end
301 end
302 device ref xhci on
303 chip drivers/usb/acpi
304 device usb 0.0 on
305 chip drivers/usb/acpi
306 register "desc" = ""USB2 Type-A Front Left""
307 register "type" = "UPC_TYPE_A"
308 register "group" = "ACPI_PLD_GROUP(0, 0)"
309 device usb 2.0 on end
310 end
311 chip drivers/usb/acpi
312 register "desc" = ""USB2 Type-C Port Rear""
313 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
314 register "group" = "ACPI_PLD_GROUP(1, 3)"
315 device usb 2.1 on end
316 end
317 chip drivers/usb/acpi
318 register "desc" = ""USB2 Type-A Front Right""
319 register "type" = "UPC_TYPE_A"
320 register "group" = "ACPI_PLD_GROUP(0, 1)"
321 device usb 2.2 on end
322 end
323 chip drivers/usb/acpi
324 register "desc" = ""USB2 Type-A Rear Right""
325 register "type" = "UPC_TYPE_A"
326 register "group" = "ACPI_PLD_GROUP(1, 2)"
327 device usb 2.3 on end
328 end
329 chip drivers/usb/acpi
330 register "desc" = ""USB2 Type-A Rear Middle""
331 register "type" = "UPC_TYPE_A"
332 register "group" = "ACPI_PLD_GROUP(1, 1)"
333 device usb 2.4 on end
334 end
335 chip drivers/usb/acpi
336 register "desc" = ""USB2 Type-A Rear Left""
337 register "type" = "UPC_TYPE_A"
338 register "group" = "ACPI_PLD_GROUP(1, 0)"
339 device usb 2.5 on end
340 end
341 chip drivers/usb/acpi
342 device usb 2.6 off end
343 end
344 chip drivers/usb/acpi
345 register "desc" = ""USB3 Type-A Front Left""
346 register "type" = "UPC_TYPE_USB3_A"
347 register "group" = "ACPI_PLD_GROUP(0, 0)"
348 device usb 3.0 on end
349 end
350 chip drivers/usb/acpi
351 register "desc" = ""USB3 Type-A Front Right""
352 register "type" = "UPC_TYPE_USB3_A"
353 register "group" = "ACPI_PLD_GROUP(0, 1)"
354 device usb 3.1 on end
355 end
356 chip drivers/usb/acpi
357 register "desc" = ""USB3 Type-A Rear Right""
358 register "type" = "UPC_TYPE_USB3_A"
359 register "group" = "ACPI_PLD_GROUP(1, 2)"
360 device usb 3.2 on end
361 end
362 chip drivers/usb/acpi
363 register "desc" = ""USB3 Type-C Rear""
364 register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
365 register "group" = "ACPI_PLD_GROUP(1, 3)"
366 device usb 3.3 on end
367 end
368 chip drivers/usb/acpi
369 register "desc" = ""USB3 Type-A Rear Left""
370 register "type" = "UPC_TYPE_USB3_A"
371 register "group" = "ACPI_PLD_GROUP(1, 0)"
372 device usb 3.4 on end
373 end
374 chip drivers/usb/acpi
375 register "desc" = ""USB3 Type-A Rear Middle""
376 register "type" = "UPC_TYPE_USB3_A"
377 register "group" = "ACPI_PLD_GROUP(1, 1)"
378 device usb 3.5 on end
379 end
380 end
381 end
382 end
383 device ref i2c2 on
384 # PCON PS175
385 chip drivers/i2c/generic
386 register "hid" = ""1AF80175""
387 register "name" = ""PS17""
388 register "desc" = ""Parade PS175""
389 device i2c 4a hidden end
390 end
391 end
392 device ref i2c3 on
393 # Realtek RTD2142
394 chip drivers/i2c/generic
395 register "hid" = ""10EC2142""
396 register "name" = ""RTD2""
397 register "desc" = ""Realtek RTD2142""
398 device i2c 4a hidden end
399 end
400 end
401 device ref i2c4 on
402 chip drivers/i2c/generic
403 register "hid" = ""10EC5682""
404 register "name" = ""RT58""
405 register "desc" = ""Realtek RT5682""
406 register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_H0)"
407 register "property_count" = "1"
408 # Set the jd_src to RT5668_JD1 for jack detection
409 register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER"
410 register "property_list[0].name" = ""realtek,jd-src""
411 register "property_list[0].integer" = "1"
412 device i2c 1a on end
413 end
414 end
415 device ref pcie_rp7 on
416 # LAN
417 chip drivers/net # RTL8111H Ethernet NIC
418 register "customized_leds" = "0x05af"
419 register "wake" = "GPE0_DW1_07" # GPP_C7
420 register "device_index" = "0"
421 register "enable_aspm_l1_2" = "1"
422 device pci 00.0 on end
423 end
424 end
425 device ref pcie_rp8 on
426 # WLAN
427 register "PcieRpSlotImplemented[7]" = "1" # M.2 Slot
428 end
429 device ref pcie_rp9 on
430 # TPU
431 register "PcieRpSlotImplemented[8]" = "1" # M.2 Slot
432 end
433 device ref pcie_rp11 on
434 # TPU1
435 register "PcieRpSlotImplemented[10]" = "1" # M.2 Slot
436 end
437 device ref pcie_rp12 on
438 # TPU0
439 register "PcieRpSlotImplemented[11]" = "1" # M.2 Slot
440 end
441 device ref pcie_rp13 on
442 # X4 i350 NIC
443 register "PcieRpSlotImplemented[12]" = "0" # Built-in
444 end
445 device ref pcie_rp14 on end # non-root
446 device ref pcie_rp15 on end # non-root
447 device ref pcie_rp16 on end # non-root
448 device ref uart1 on end
449 end
450
451 # VR Settings Configuration for 4 Domains
452 #+----------------+-------+-------+-------+-------+
453 #| Domain/Setting | SA | IA | GTUS | GTS |
454 #+----------------+-------+-------+-------+-------+
455 #| Psi1Threshold | 20A | 20A | 20A | 20A |
456 #| Psi2Threshold | 5A | 5A | 5A | 5A |
457 #| Psi3Threshold | 1A | 1A | 1A | 1A |
458 #| Psi3Enable | 1 | 1 | 1 | 1 |
459 #| Psi4Enable | 1 | 1 | 1 | 1 |
460 #| ImonSlope | 0 | 0 | 0 | 0 |
461 #| ImonOffset | 0 | 0 | 0 | 0 |
462 #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
463 #| AcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
464 #| DcLoadline | 10.04 | 1.81 | 3.19 | 3.19 |
465 #+----------------+-------+-------+-------+-------+
466 #Note: IccMax settings are moved to SoC code
467 register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
468 .vr_config_enable = 1,
469 .psi1threshold = VR_CFG_AMP(20),
470 .psi2threshold = VR_CFG_AMP(5),
471 .psi3threshold = VR_CFG_AMP(1),
472 .psi3enable = 1,
473 .psi4enable = 1,
474 .imon_slope = 0x0,
475 .imon_offset = 0x0,
476 .icc_max = 0,
477 .voltage_limit = 1520,
478 .ac_loadline = 1004,
479 .dc_loadline = 1004,
480 }"
481
482 register "domain_vr_config[VR_IA_CORE]" = "{
483 .vr_config_enable = 1,
484 .psi1threshold = VR_CFG_AMP(20),
485 .psi2threshold = VR_CFG_AMP(5),
486 .psi3threshold = VR_CFG_AMP(1),
487 .psi3enable = 1,
488 .psi4enable = 1,
489 .imon_slope = 0x0,
490 .imon_offset = 0x0,
491 .icc_max = 0,
492 .voltage_limit = 1520,
493 .ac_loadline = 181,
494 .dc_loadline = 181,
495 }"
496
497 register "domain_vr_config[VR_GT_UNSLICED]" = "{
498 .vr_config_enable = 1,
499 .psi1threshold = VR_CFG_AMP(20),
500 .psi2threshold = VR_CFG_AMP(5),
501 .psi3threshold = VR_CFG_AMP(1),
502 .psi3enable = 1,
503 .psi4enable = 1,
504 .imon_slope = 0x0,
505 .imon_offset = 0x0,
506 .icc_max = 0,
507 .voltage_limit = 1520,
508 .ac_loadline = 319,
509 .dc_loadline = 319,
510 }"
511
512 register "domain_vr_config[VR_GT_SLICED]" = "{
513 .vr_config_enable = 1,
514 .psi1threshold = VR_CFG_AMP(20),
515 .psi2threshold = VR_CFG_AMP(5),
516 .psi3threshold = VR_CFG_AMP(1),
517 .psi3enable = 1,
518 .psi4enable = 1,
519 .imon_slope = 0x0,
520 .imon_offset = 0x0,
521 .icc_max = 0,
522 .voltage_limit = 1520,
523 .ac_loadline = 319,
524 .dc_loadline = 319,
525 }"
526
527 end
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