src/mainboard/google/puff/variants/scout/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <commonlib/helpers.h>
   6
   7 static const struct pad_config gpio_table[] = {
   8         /* A16 : SD_OC_ODL */
   9         PAD_CFG_GPI(GPP_A16, NONE, DEEP),
  10         /* A18 : LAN_PE_ISOLATE_ODL */
  11         PAD_CFG_GPO(GPP_A18, 1, DEEP),
  12         /* A19 : Not connected */
  13         PAD_NC(GPP_A19, NONE),
  14         /* A20 : Not connected */
  15         PAD_NC(GPP_A20, NONE),
  16         /* A23 : M2_WLAN_INT_ODL */
  17         PAD_CFG_GPI_APIC(GPP_A23, NONE, PLTRST, LEVEL, INVERT),
  18
  19         /* B5 : LAN_CLKREQ_ODL */
  20         PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
  21         /* B6 : M2_SSD_CLKREQ_ODL */
  22         PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
  23         /* B7 : M2_TPU0_CLKREQ_ODL */
  24         PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
  25         /* B8 : CLK_PCIE_REQ3 (not connected) */
  26         PAD_NC(GPP_B8, NONE),
  27         /* B9 : M2_TPU1_CLKREQ_ODL */
  28         PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
  29         /* B10 : M2_WLAN_CLKREQ_ODL */
  30         PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1),
  31
  32         /* C0 : SMBCLK */
  33         PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
  34         /* C1 : SMBDATA */
  35         PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
  36         /* C3  : PCH_MBCLK1_R (i350) */
  37         PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1),
  38         /* C4  : PCH_MBDAT1_R (i350) */
  39         PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1),
  40         /* C6: M2_WLAN_WAKE_ODL */
  41         PAD_CFG_GPI_SCI_LOW(GPP_C6, NONE, DEEP, EDGE_SINGLE),
  42         /* C7 : LAN_WAKE_ODL */
  43         PAD_CFG_GPI_SCI_LOW(GPP_C7, NONE, DEEP, EDGE_SINGLE),
  44         /* C10 : PCH_PCON_RST_ODL */
  45         PAD_CFG_GPO(GPP_C10, 1, DEEP),
  46         /* C11 : PCH_PCON1_PDB_ODL */
  47         PAD_CFG_GPO(GPP_C11, 1, DEEP),
  48         /* C12 : PCH_RX_TSUM_UART_TX */
  49         PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
  50         /* C13 : PCH_RX_TSUM_UART_RX */
  51         PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
  52         /* C15  : WLAN_OFF_L */
  53         PAD_CFG_GPO(GPP_C15, 1, DEEP),
  54         /* C16 : PCH_I2C_RFU_SDA (NC) */
  55         PAD_NC(GPP_C16, NONE),
  56         /* C17 : PCH_I2C_RFU_SCL (NC) */
  57         PAD_NC(GPP_C17, NONE),
  58         /* C18 : PCH_I2C_USI_SDA */
  59         PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1),
  60         /* C19 : PCH_I2C_USI_SDL */
  61         PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
  62
  63         /* D13  : SMBUS_ISP_SCALAR */
  64         PAD_CFG_GPO(GPP_D13, 0, DEEP),
  65         /* D14 : EC_PCH_INT_L */
  66         PAD_CFG_GPI_APIC(GPP_D14, NONE, PLTRST, LEVEL, INVERT),
  67         /* D15 : USI_RST_L */
  68         PAD_CFG_GPO(GPP_D15, 1, DEEP),
  69         /* D16 TOUCH_INT */
  70         PAD_CFG_GPI_IRQ_WAKE(GPP_D16, NONE, PLTRST, LEVEL, INVERT),
  71
  72         /* E2 : Not connected */
  73         PAD_NC(GPP_E2, NONE),
  74         /* E3 : TPU_RST_PIN40 */
  75         PAD_CFG_GPO(GPP_E3, 1, DEEP),
  76         /* E7 : TPU_RST_PIN42 */
  77         PAD_CFG_GPO(GPP_E7, 1, DEEP),
  78         /* E9 : PU 10K to PP3300_SOC_A */
  79         PAD_NC(GPP_E9, NONE),
  80         /* E10 : USB_A1_OC_ODL */
  81         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
  82         /* E15 : PCH_TYPEC_UPFB */
  83         PAD_CFG_GPI(GPP_E15, NONE, DEEP),
  84
  85         /* E18 : DDI1_CLK */
  86         PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
  87         /* E19 : DDI1_DATA */
  88         PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
  89
  90         /* F11 : EMMC_CMD */
  91         PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
  92         /* F12 : EMMC_DATA0 */
  93         PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
  94         /* F13 : EMMC_DATA1 */
  95         PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
  96         /* F14 : EMMC_DATA2 */
  97         PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
  98         /* F15 : EMMC_DATA3 */
  99         PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
 100         /* F16 : EMMC_DATA4 */
 101         PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
 102         /* F17 : EMMC_DATA5 */
 103         PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
 104         /* F18 : EMMC_DATA6 */
 105         PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
 106         /* F19 : EMMC_DATA7 */
 107         PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
 108         /* F20 : EMMC_RCLK */
 109         PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
 110         /* F21 : EMMC_CLK */
 111         PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
 112         /* F22 : EMMC_RST_L */
 113         PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
 114
 115         /* H4: PCH_I2C_SCALER_SDA */
 116         PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1),
 117         /* H5: PCH_I2C_SCALER_SCL */
 118         PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1),
 119         /* H6  : PCH_I2C_TPU_SDA */
 120         PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
 121         /* H7  : PCH_I2C_TPU_SCL */
 122         PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1),
 123         /* H8  : NC */
 124         PAD_NC(GPP_H8, NONE),
 125         /* H9  : NC */
 126         PAD_NC(GPP_H9, NONE),
 127         /* H10 : NC */
 128         PAD_NC(GPP_H10, NONE),
 129         /* H11 : NC */
 130         PAD_NC(GPP_H11, NONE),
 131         /* H22 : PWM_PP3300_BIOZZER */
 132         PAD_CFG_GPO(GPP_H22, 0, DEEP),
 133 };
 134
 135 const struct pad_config *override_gpio_table(size_t *num)
 136 {
 137         *num = ARRAY_SIZE(gpio_table);
 138         return gpio_table;
 139 }
 140
 141 /* Early pad configuration in bootblock */
 142 static const struct pad_config early_gpio_table[] = {
 143         /* B14 : GPP_B14_STRAP */
 144         PAD_NC(GPP_B14, NONE),
 145         /* B22 : GPP_B22_STRAP */
 146         PAD_NC(GPP_B22, NONE),
 147         /* E19 : GPP_E19_STRAP */
 148         PAD_NC(GPP_E19, NONE),
 149         /* E21 : GPP_E21_STRAP */
 150         PAD_NC(GPP_E21, NONE),
 151         /* B15 : H1_SLAVE_SPI_CS_L */
 152         PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1),
 153         /* B16 : H1_SLAVE_SPI_CLK */
 154         PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1),
 155         /* B17 : H1_SLAVE_SPI_MISO_R */
 156         PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1),
 157         /* B18 : H1_SLAVE_SPI_MOSI_R */
 158         PAD_CFG_NF(GPP_B18, NONE, DEEP, NF1),
 159         /* C8  : UART_PCH_RX_DEBUG_TX */
 160         PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1),
 161         /* C9  : UART_PCH_TX_DEBUG_RX */
 162         PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1),
 163         /* C14 : BT_DISABLE_L */
 164         PAD_CFG_GPO(GPP_C14, 0, DEEP),
 165         /* PCH_WP_OD */
 166         PAD_CFG_GPI(GPP_C20, NONE, DEEP),
 167         /* C21 : H1_PCH_INT_ODL */
 168         PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT),
 169         /* C22 : EC_IN_RW_OD */
 170         PAD_CFG_GPI(GPP_C22, NONE, DEEP),
 171         /* C23 : WLAN_PE_RST# */
 172         PAD_CFG_GPO(GPP_C23, 1, DEEP),
 173         /* E1  : M2_SSD_PEDET */
 174         PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 175         /* E5  : SATA_DEVSLP1 */
 176         PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
 177 };
 178
 179 const struct pad_config *variant_early_gpio_table(size_t *num)
 180 {
 181         *num = ARRAY_SIZE(early_gpio_table);
 182         return early_gpio_table;
 183 }