src/mainboard/google/rambi/devicetree.cb

   1 chip soc/intel/baytrail
   2
   3         # IGD Displays
   4         register "gfx" = "GMA_STATIC_DISPLAYS(0)"
   5
   6         # SATA port enable mask (2 ports)
   7         register "sata_port_map" = "0x1"
   8         register "sata_ahci" = "0x1"
   9         register "ide_legacy_combined" = "0x0"
  10
  11         # Route USB ports to XHCI
  12         register "usb_route_to_xhci" = "1"
  13
  14         # USB Port Disable Mask
  15         register "usb2_port_disable_mask" = "0x0"
  16         register "usb3_port_disable_mask" = "0x0"
  17
  18         # USB PHY settings
  19         register "usb2_per_port_lane0" = "0x00049a09"
  20         register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d"
  21         register "usb2_per_port_lane1" = "0x00049a09"
  22         register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d"
  23         register "usb2_per_port_lane2" = "0x00049209"
  24         register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015"
  25         register "usb2_per_port_lane3" = "0x00049a09"
  26         register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d"
  27
  28         # LPE audio codec settings
  29         register "lpe_codec_clk_freq" = "25" # 25MHz clock
  30         register "lpe_codec_clk_num" = "0"   # PMC_PLT_CLK[0]
  31
  32         # SD Card controller
  33         register "sdcard_cap_low" = "0x036864b2"
  34         register "sdcard_cap_high" = "0x0"
  35
  36         # Enable devices in ACPI mode
  37         register "lpe_acpi_mode" = "1"
  38         register "lpss_acpi_mode" = "1"
  39         register "scc_acpi_mode" = "1"
  40
  41         # Enable PIPEA as DP_C
  42         register "gpu_pipea_port_select" = "2"          # DP_C
  43         register "gpu_pipea_power_cycle_delay" = "6"    # 600ms
  44         register "gpu_pipea_power_on_delay" = "5000"    # 500ms
  45         register "gpu_pipea_light_on_delay" = "70"      # 7ms
  46         register "gpu_pipea_power_off_delay" = "500"    # 50ms
  47         register "gpu_pipea_light_off_delay" = "2000"   # 200ms
  48
  49         # VR PS2 control
  50         register "vnn_ps2_enable" = "1"
  51         register "vcc_ps2_enable" = "1"
  52
  53         # Disable SLP_X stretching after SUS power well fail.
  54         register "disable_slp_x_stretch_sus_fail" = "1"
  55
  56         device cpu_cluster 0 on end
  57         device domain 0 on
  58                 device pci 00.0 on  end # SoC router
  59                 device pci 02.0 on  end # GFX
  60                 device pci 10.0 off end # MMC
  61                 device pci 11.0 off end # SDIO
  62                 device pci 12.0 on  end # SD
  63                 device pci 13.0 on  end # SATA
  64                 device pci 14.0 on  end # XHCI
  65                 device pci 15.0 on  end # LPE
  66                 device pci 17.0 on  end # MMC45
  67                 device pci 18.0 on  end # SIO_DMA1
  68                 device pci 18.1 on  end # I2C1
  69                 device pci 18.2 on  end # I2C2
  70                 device pci 18.3 off end # I2C3
  71                 device pci 18.4 off end # I2C4
  72                 device pci 18.5 off end # I2C5
  73                 device pci 18.6 off end # I2C6
  74                 device pci 18.7 off end # I2C7
  75                 device pci 1a.0 off end # TXE
  76                 device pci 1b.0 on  end # HDA
  77                 device pci 1c.0 on  end # PCIE_PORT1
  78                 device pci 1c.1 off end # PCIE_PORT2
  79                 device pci 1c.2 off end # PCIE_PORT3
  80                 device pci 1c.3 off end # PCIE_PORT4
  81                 device pci 1d.0 on  end # EHCI
  82                 device pci 1e.0 on  end # SIO_DMA2
  83                 device pci 1e.1 off end # PWM1
  84                 device pci 1e.2 off end # PWM2
  85                 device pci 1e.3 off end # HSUART1
  86                 device pci 1e.4 off end # HSUART2
  87                 device pci 1e.5 off end # SPI
  88                 device pci 1f.0 on
  89                         chip drivers/pc80/tpm
  90                                 device pnp 0c31.0 on end
  91                         end
  92                         chip ec/google/chromeec
  93                                 # We only have one init function that
  94                                 # we need to call to initialize the
  95                                 # keyboard part of the EC.
  96                                 device pnp ff.1 on # dummy address
  97                                 end
  98                         end
  99                 end # LPC Bridge
 100                 device pci 1f.3 off end # SMBus
 101         end
 102 end