src/mainboard/google/reef/chromeos.fmd

   1 FLASH 16M {
   2         WP_RO@0x0 0x400000 {
   3                 SI_DESC@0x0 0x1000
   4                 IFWI@0x1000 0x1ff000
   5                 RO_VPD(PRESERVE)@0x200000 0x4000
   6                 RO_SECTION@0x204000 0x1fc000 {
   7                         FMAP@0x0 0x800
   8                         RO_FRID@0x800 0x40
   9                         RO_FRID_PAD@0x840 0x7c0
  10                         COREBOOT(CBFS)@0x1000 0x1bb000
  11                         GBB@0x1bc000 0x40000
  12                 }
  13         }
  14         MISC_RW@0x400000 0x30000 {
  15                 UNIFIED_MRC_CACHE@0x0 0x21000 {
  16                         RECOVERY_MRC_CACHE@0x0 0x10000
  17                         RW_MRC_CACHE@0x10000 0x10000
  18                         RW_VAR_MRC_CACHE@0x20000 0x1000
  19                 }
  20                 RW_ELOG(PRESERVE)@0x21000 0x3000
  21                 RW_SHARED@0x24000 0x4000 {
  22                         SHARED_DATA@0x0 0x2000
  23                         VBLOCK_DEV@0x2000 0x2000
  24                 }
  25                 RW_VPD(PRESERVE)@0x28000 0x2000
  26                 RW_NVRAM(PRESERVE)@0x2a000 0x5000
  27                 FPF_STATUS@0x2f000 0x1000
  28         }
  29         RW_SECTION_A@0x430000 0x480000 {
  30                 VBLOCK_A@0x0 0x10000
  31                 FW_MAIN_A(CBFS)@0x10000 0x46ffc0
  32                 RW_FWID_A@0x47ffc0 0x40
  33         }
  34         RW_SECTION_B@0x8b0000 0x480000 {
  35                 VBLOCK_B@0x0 0x10000
  36                 FW_MAIN_B(CBFS)@0x10000 0x46ffc0
  37                 RW_FWID_B@0x47ffc0 0x40
  38         }
  39         SMMSTORE(PRESERVE)@0xd30000 0x40000
  40         RW_LEGACY(CBFS)@0xd70000 0x1c0000
  41         BIOS_UNUSABLE@0xf30000 0x4f000
  42         DEVICE_EXTENSION@0xf7f000 0x80000
  43         # Currently, it is required that the BIOS region be a multiple of 8KiB.
  44         # This is required so that the recovery mechanism can find SIGN_CSE
  45         # region aligned to 4K at the center of BIOS region. Since the
  46         # descriptor at the beginning uses 4K and BIOS starts at an offset of
  47         # 4K, a hole of 4K is created towards the end of the flash to compensate
  48         # for the size requirement of BIOS region.
  49         # FIT tool thus creates descriptor with following regions:
  50         # Descriptor --> 0 to 4K
  51         # BIOS       --> 4K to 0xf7f000
  52         # Device ext --> 0xf7f000 to 0xfff000
  53         UNUSED_HOLE@0xfff000 0x1000
  54 }