src/mainboard/google/sarien/variants/arcada/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2
   3 #include <variant/gpio.h>
   4 #include <vendorcode/google/chromeos/chromeos.h>
   5
   6 /* Pad configuration in ramstage */
   7 static const struct pad_config gpio_table[] = {
   8 /* RCIN# */             PAD_NC(GPP_A0, NONE),
   9 /* ESPI_IO0 */
  10 /* ESPI_IO1 */
  11 /* ESPI_IO2 */
  12 /* ESPI_IO3 */
  13 /* ESPI_CS# */
  14 /* SERIRQ */
  15 /* PIRQA# */            PAD_NC(GPP_A7, NONE),
  16 /* CLKRUN# */           PAD_NC(GPP_A8, NONE),
  17 /* ESPI_CLK */
  18 /* CLKOUT_LPC1 */       PAD_NC(GPP_A10, NONE),
  19 /* PME# */              PAD_NC(GPP_A11, NONE),
  20                         /* ISH_LID_CL#_TAB */
  21 /* ISH_GP6 */           PAD_CFG_NF(GPP_A12, NONE, DEEP, NF2),
  22 /* SUSWARN# */          PAD_NC(GPP_A13, NONE),
  23 /* ESPI_RESET# */
  24 /* SUSACK# */           PAD_NC(GPP_A15, NONE),
  25 /* SD_1P8_SEL */        PAD_NC(GPP_A16, NONE),
  26 /* SD_PWR_EN# */        PAD_NC(GPP_A17, NONE),
  27                         /* ISH_ACC1_INT# */
  28 /* ISH_GP0 */           PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
  29                         /* ISH_ACC2_INT# */
  30 /* ISH_GP1 */           PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1),
  31 /* ISH_GP2 */           PAD_NC(GPP_A20, NONE),
  32 /* ISH_GP3 */           PAD_NC(GPP_A21, NONE),
  33                         /* ISH_NB_MODE */
  34 /* ISH_GP4 */           PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
  35                         /* ISH_LID_CL#_NB */
  36 /* ISH_GP5 */           PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1),
  37
  38 /* CORE_VID0 */
  39 /* CORE_VID1 */
  40 /* VRALERT# */          PAD_NC(GPP_B2, NONE),
  41 /* CPU_GP2 */           PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST,
  42                                  LEVEL, INVERT), /* TOUCHPAD_INTR# */
  43 /* CPU_GP3 */           PAD_CFG_GPI(GPP_B4, NONE, DEEP), /* TOUCH_SCREEN_DET# */
  44                          /* LAN_CLKREQ_CPU_N */
  45 /* SRCCLKREQ0# */       PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1),
  46                         /* CARD_CLKREQ_CPU_N */
  47 /* SRCCLKREQ1# */       PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
  48                         /* WLAN_CLKREQ_CPU_N */
  49 /* SRCCLKREQ2# */       PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
  50                         /* WWAN_CLKREQ_CPU_N */
  51 /* SRCCLKREQ3# */       PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1),
  52                         /* SSD_CKLREQ_CPU_N */
  53 /* SRCCLKREQ4# */       PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
  54 /* SRCCLKREQ5# */       PAD_NC(GPP_B10, NONE), /* TBT_CLKREQ_CPU_N (nostuff) */
  55 /* EXT_PWR_GATE# */     PAD_CFG_GPO(GPP_B11, 0, DEEP), /* 3.3V_CAM_EN# */
  56 /* SLP_S0# */           PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
  57 /* PLTRST# */           PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
  58 /* SPKR */              PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1),
  59 /* GSPI0_CS# */         PAD_NC(GPP_B15, NONE), /* PRIM_CORE_OPT_DIS (nostuff) */
  60 /* GSPI0_CLK */         PAD_CFG_GPI(GPP_B16, NONE, DEEP), /* ONE_DIMM# */
  61 /* GSPI0_MISO */        PAD_NC(GPP_B17, NONE), /* RTC_DET# */
  62 /* GSPI0_MOSI */        PAD_NC(GPP_B18, NONE),
  63 /* GSPI1_CS# */         PAD_NC(GPP_B19, NONE), /* HDD_FALL_INT (nostuff) */
  64 /* GSPI1_CLK */         PAD_NC(GPP_B20, NONE), /* TPM_PIRQ# (nostuff) */
  65 /* GSPI1_MISO */        PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
  66 /* GSPI1_MOSI */        PAD_NC(GPP_B22, NONE),
  67 /* SML1ALERT# */        PAD_NC(GPP_B23, DN_20K),
  68
  69 /* SMBCLK */            PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* MEM_SMBCLK */
  70 /* SMBDATA */           PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* MEM_SMBDATA */
  71 /* SMBALERT# */         PAD_NC(GPP_C2, DN_20K),
  72 /* SML0CLK */           PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_SMBCLK */
  73 /* SML0DATA */          PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_SMBDATA */
  74 /* SML0ALERT# */        PAD_NC(GPP_C5, DN_20K),
  75 /* SM1CLK */            PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* SML1_SMBCLK */
  76 /* SM1DATA */           PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* SML1_SMBDATA */
  77 /* UART0_RXD */         PAD_NC(GPP_C8, NONE), /* PCH_TBT_PERST# (nostuff) */
  78 /* UART0_TXD */         PAD_NC(GPP_C9, NONE),
  79 /* UART0_RTS# */        PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */
  80 /* UART0_CTS# */        PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */
  81 /* UART1_RXD */         PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,
  82                                     EDGE_SINGLE), /* SIO_EXT_WAKE# */
  83 /* UART1_TXD */         PAD_NC(GPP_C13, NONE),
  84 /* UART1_RTS# */        PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */
  85 /* UART1_CTS# */        PAD_NC(GPP_C15, NONE),
  86 /* I2C0_SDA */          PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */
  87 /* I2C0_SCL */          PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TS_I2C_SCL */
  88 /* I2C1_SDA */          PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SDA_TP */
  89 /* I2C1_SCL */          PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* I2C1_SCK_TP */
  90 /* UART2_RXD */         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
  91 /* UART2_TXD */         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
  92 /* UART2_RTS# */        PAD_NC(GPP_C22, NONE),
  93 /* UART2_CTS# */        PAD_CFG_GPI_APIC(GPP_C23, NONE, PLTRST,
  94                                  LEVEL, NONE), /* TS_INT# */
  95
  96 /* SPI1_CS# */          PAD_CFG_GPI_APIC(GPP_D0, NONE, PLTRST,
  97                                  EDGE_SINGLE, INVERT), /* MEDIACARD_IRQ# */
  98 /* SPI1_CLK */          PAD_NC(GPP_D1, NONE),
  99 /* SPI1_MISO */         PAD_CFG_GPI(GPP_D2, NONE, DEEP), /* ISH_LAN# */
 100 /* SPI1_MOSI */         PAD_NC(GPP_D3, NONE),
 101 /* FASHTRIG */          PAD_NC(GPP_D4, NONE), /* TBT_FORCE_PWR (nostuff) */
 102                         /* ISH_I2C0_ACC_SDA */
 103 /* ISH_I2C0_SDA */      PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1),
 104                         /* ISH_I2C0_ACC_SCL */
 105 /* ISH_I2C0_SCL */      PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
 106 /* ISH_I2C1_SDA */      PAD_NC(GPP_D7, NONE),
 107 /* ISH_I2C1_SCL */      PAD_NC(GPP_D8, NONE),
 108 /* ISH_SPI_CS# */       PAD_CFG_GPI(GPP_D9, NONE, DEEP), /* IR_CAM_DET# */
 109 /* ISH_SPI_CLK */       PAD_NC(GPP_D10, NONE),
 110 /* ISH_SPI_MISO */      PAD_CFG_GPI(GPP_D11, NONE, DEEP), /* TBT_DET# */
 111 /* ISH_SPI_MOSI */      PAD_NC(GPP_D12, NONE),
 112                         /* ISH_CPU_UART0_RX */
 113 /* ISH_UART0_RXD */     PAD_CFG_NF(GPP_D13, UP_20K, DEEP, NF1),
 114                         /* ISH_CPU_UART0_TX */
 115 /* ISH_UART0_TXD */     PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1),
 116 /* ISH_UART0_RTS# */    PAD_CFG_GPO(GPP_D15, 1, DEEP), /* WWAN_FULL_PWR_EN */
 117 /* ISH_UART0_CTS# */    PAD_NC(GPP_D16, NONE),
 118 /* DMIC_CLK1 */         PAD_CFG_GPI(GPP_D17, NONE, DEEP), /* KB_DET# */
 119 /* DMIC_DATA1 */        PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
 120                                  EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
 121 /* DMIC_CLK0 */         PAD_NC(GPP_D19, NONE),
 122 /* DMIC_DATA0 */        PAD_NC(GPP_D20, NONE),
 123 /* SPI1_IO2 */          PAD_CFG_GPO(GPP_D21, 1, DEEP), /* WWAN_BB_RST# */
 124 /* SPI1_IO3 */          PAD_CFG_GPO(GPP_D22, 0, DEEP), /* WWAN_GPIO_PERST# */
 125 /* I2S_MCLK */          PAD_CFG_GPI_SCI_LOW(GPP_D23, NONE, DEEP,
 126                                  EDGE_SINGLE), /* WWAN_GPIO_WAKE# */
 127
 128 /* SATAXPCIE0 */        PAD_NC(GPP_E0, NONE),
 129                         /* M3042_PCIE#_SATA */
 130 /* SATAXPCIE1 */        PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1),
 131                         /* M2880_PCIE_SATA# */
 132 /* SATAXPCIE2 */        PAD_CFG_NF(GPP_E2, NONE, DEEP, NF1),
 133 /* CPU_GP0 */           PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
 134 /* SATA_DEVSLP0 */      PAD_NC(GPP_E4, NONE),
 135 /* SATA_DEVSLP1 */      PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), /* M3042_DEVSLP */
 136 /* SATA_DEVSLP2 */      PAD_CFG_NF(GPP_E6, NONE, DEEP, NF1), /* M2280_DEVSLP */
 137 /* CPU_GP1 */           PAD_CFG_GPO(GPP_E7, 1, DEEP), /* TOUCH_SCREEN_PD# */
 138 /* SATALED# */          PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
 139 /* USB2_OCO# */         PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB_OC0# */
 140 /* USB2_OC1# */         PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB_OC1# */
 141 /* USB2_OC2# */         PAD_NC(GPP_E11, NONE),
 142 /* USB2_OC3# */         PAD_NC(GPP_E12, NONE),
 143 /* DDPB_HPD0 */         PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DP_HPD_CPU */
 144 /* DDPC_HPD1 */         PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DP2_HPD_CPU */
 145 /* DDPD_HPD2 */         PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
 146 /* DDPE_HPD3 */         PAD_NC(GPP_E16, NONE), /* FFS_INT2 (nostuff) */
 147 /* EDP_HPD */           PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
 148 /* DDPB_CTRLCLK */      PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* HDMI_SCL_CPU */
 149 /* DDPB_CTRLDATA */     PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* HDMI_SDA_CPU */
 150 /* DDPC_CTRLCLK */      PAD_NC(GPP_E20, NONE),
 151 /* DDPC_CTRLDATA */     PAD_NC(GPP_E21, NONE),
 152 /* DDPD_CTRLCLK */      PAD_NC(GPP_E22, NONE),
 153 /* DDPD_CTRLDATA */     PAD_NC(GPP_E23, NONE),
 154
 155 /* CNV_PA_BLANKING */   PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), /* CNV_COEX3 */
 156 /* GPP_F1 */            PAD_NC(GPP_F1, NONE),
 157 /* GPP_F2 */            PAD_NC(GPP_F2, NONE),
 158 /* GPP_F3 */            PAD_NC(GPP_F3, NONE),
 159 /* CNV_BRI_DT */        PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1),
 160 /* CNV_BRI_RSP */       PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1),
 161 /* CNV_RGI_DT */        PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1),
 162 /* CNV_RGI_RSP */       PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1),
 163 /* CNV_MFUART2_RXD */   PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* CNV_COEX2 */
 164 /* CNV_MFUART2_TXD */   PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* CNV_COEX1 */
 165 /* GPP_F10 */           PAD_NC(GPP_F10, NONE),
 166 /* EMMC_CMD */          PAD_NC(GPP_F11, NONE),
 167 /* EMMC_DATA0 */        PAD_NC(GPP_F12, NONE),
 168 /* EMMC_DATA1 */        PAD_NC(GPP_F13, NONE),
 169 /* EMMC_DATA2 */        PAD_NC(GPP_F14, NONE),
 170 /* EMMC_DATA3 */        PAD_NC(GPP_F15, NONE),
 171 /* EMMC_DATA4 */        PAD_NC(GPP_F16, NONE),
 172 /* EMMC_DATA5 */        PAD_NC(GPP_F17, NONE),
 173 /* EMMC_DATA6 */        PAD_NC(GPP_F18, NONE),
 174 /* EMMC_DATA7 */        PAD_NC(GPP_F19, NONE),
 175 /* EMMC_RCLK */         PAD_NC(GPP_F20, NONE),
 176 /* EMMC_CLK */          PAD_NC(GPP_F21, NONE),
 177 /* EMMC_RESET# */       PAD_NC(GPP_F22, NONE),
 178 /* A4WP_PRESENT */      PAD_NC(GPP_F23, NONE),
 179
 180 /* SD_CMD */            PAD_CFG_GPI(GPP_G0, NONE, DEEP), /* CAM_MIC_CBL_DET# */
 181 /* SD_DATA0 */          PAD_NC(GPP_G1, NONE), /* ANT_CONFIG (nostuff) */
 182 /* SD_DATA1 */          PAD_NC(GPP_G2, NONE), /* TBT_CIO_PLUG_EVT# (nostuff) */
 183 /* SD_DATA2 */          PAD_NC(GPP_G3, NONE),
 184 /* SD_DATA3 */          PAD_CFG_GPI(GPP_G4, NONE, DEEP), /* CTLESS_DET# */
 185 /* SD_CD# */            PAD_CFG_GPO(GPP_G5, 1, DEEP), /* HOST_SD_WP# */
 186 /* SD_CLK */            PAD_CFG_GPO(GPP_G6, 1, DEEP), /* AUD_PWR_EN */
 187 /* SD_WP */             PAD_CFG_GPI(GPP_G7, NONE, DEEP), /* SPK_DET# */
 188
 189 /* I2S2_SCLK */         PAD_NC(GPP_H0, NONE),
 190 /* I2S2_SFRM */         PAD_CFG_NF(GPP_H1, NONE, DEEP, NF3), /* CNV_RF_RESET# */
 191 /* I2S2_TXD */          PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* CLKREQ_CNV# */
 192 /* I2S2_RXD */          PAD_NC(GPP_H3, NONE),
 193 /* I2C2_SDA */          PAD_NC(GPP_H4, NONE),
 194 /* I2C2_SCL */          PAD_NC(GPP_H5, NONE),
 195 /* I2C3_SDA */          PAD_NC(GPP_H6, NONE),
 196 /* I2C3_SCL */          PAD_NC(GPP_H7, NONE),
 197 /* I2C4_SDA */          PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
 198 /* I2C4_SCL */          PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
 199 /* I2C5_SDA */          PAD_NC(GPP_H10, NONE), /* ISH_I2C2_SDA */
 200 /* I2C5_SCL */          PAD_NC(GPP_H11, NONE), /* ISH_I2C2_SCL */
 201 /* M2_SKT2_CFG2 */      PAD_NC(GPP_H14, NONE),
 202 /* M2_SKT2_CFG3 */      PAD_CFG_GPO(GPP_H15, 1, DEEP), /* BT_RADIO_DIS# */
 203 /* DDPF_CTRLCLK */      PAD_NC(GPP_H16, NONE),
 204 /* DPPF_CTRLDATA */     PAD_NC(GPP_H17, NONE),
 205 /* CPU_C10_GATE# */     PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), /* C10_GATE# */
 206 /* TIMESYNC0 */         PAD_NC(GPP_H19, NONE),
 207 /* IMGCLKOUT1 */        PAD_NC(GPP_H20, NONE),
 208 /* GPP_H21 */           PAD_NC(GPP_H21, NONE),
 209 /* GPP_H22 */           PAD_NC(GPP_H22, NONE), /* RTD3_CIO_PWR_EN (nostuff) */
 210 /* GPP_H23 */           PAD_NC(GPP_H23, NONE),
 211
 212 /* BATLOW# */           PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* BATLOW# */
 213 /* ACPRESENT */         PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* AC_PRESENT */
 214 /* LAN_WAKE# */         PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* LAN_WAKE# */
 215 /* PWRBTN# */           PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SIO_PWRBTN# */
 216 /* SLP_S3# */           PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SIO_SLP_S3# */
 217 /* SLP_S4# */           PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* SIO_SLP_S4# */
 218 /* SLP_A# */            PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* SIO_SLP_A# */
 219 /* GPD7 */              PAD_NC(GPD7, NONE), /* TBT_RTD3_WAKE# (nostuff) */
 220 /* SUSCLK */            PAD_CFG_NF(GPD8, NONE, DEEP, NF1), /* SUSCLK */
 221 /* SLP_WLAN# */         PAD_CFG_NF(GPD9, NONE, DEEP, NF1), /* SIO_SLP_WLAN# */
 222 /* SLP_S5# */           PAD_CFG_NF(GPD10, NONE, DEEP, NF1), /* SIO_SLP_S5# */
 223 /* LANPHYC */           PAD_CFG_NF(GPD11, NONE, DEEP, NF1), /* PM_LANPHY_EN */
 224 };
 225
 226 /* Early pad configuration in bootblock */
 227 static const struct pad_config early_gpio_table[] = {
 228 /* M2_SKT2_CFG1 */      PAD_CFG_GPO(GPP_H13, 1, DEEP), /* M.2 SSD D3 cold */
 229 /* SSD RESET pin will stay low first */
 230 /* M2_SKT2_CFG0 */      PAD_CFG_GPO(GPP_H12, 0, DEEP), /* D3 cold RST */
 231 /* UART2_RXD */         PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVOTX_UART */
 232 /* UART2_TXD */         PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVORX_UART */
 233 /* I2C4_SDA */          PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), /* I2C_SDA_H1 */
 234 /* I2C4_SCL */          PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), /* I2C_SCL_H1 */
 235 /* DMIC_DATA1 */        PAD_CFG_GPI_APIC(GPP_D18, NONE, PLTRST,
 236                                  EDGE_SINGLE, INVERT), /* H1_PCH_INT_ODL */
 237 /* RESET# need to stay low before FULL_CARD_POWER_OFF assert */
 238 /* SPI1_IO2 */          PAD_CFG_GPO(GPP_D21, 0, DEEP), /* WWAN_BB_RST# */
 239 /* CPU_GP0 */           PAD_CFG_GPI(GPP_E3, NONE, DEEP), /* MEM_INTERLEAVED */
 240 /* SATALED# */          PAD_CFG_GPI(GPP_E8, NONE, DEEP), /* RECOVERY# */
 241 /* DDPD_HPD2 */         PAD_CFG_GPI(GPP_E15, NONE, DEEP), /* PCH_WP */
 242 /* M2_SKT2_CFG0 */      PAD_CFG_GPO(GPP_H12, 1, DEEP), /* D3 cold RST */
 243 };
 244
 245 static const struct pad_config romstage_gpio_table[] = {
 246         /* Enable touchscreen, hold in reset */
 247         PAD_CFG_GPO(GPP_B21, 1, DEEP), /* PCH_3.3V_TS_EN */
 248         PAD_CFG_GPO(GPP_E7, 0, DEEP), /* TOUCH_SCREEN_PD# */
 249 };
 250
 251 const struct pad_config *variant_gpio_table(size_t *num)
 252 {
 253         *num = ARRAY_SIZE(gpio_table);
 254         return gpio_table;
 255 }
 256
 257 const struct pad_config *variant_early_gpio_table(size_t *num)
 258 {
 259         *num = ARRAY_SIZE(early_gpio_table);
 260         return early_gpio_table;
 261 }
 262
 263 const struct pad_config *variant_romstage_gpio_table(size_t *num)
 264 {
 265         *num = ARRAY_SIZE(romstage_gpio_table);
 266         return romstage_gpio_table;
 267 }
 268
 269 static const struct cros_gpio cros_gpios[] = {
 270         CROS_GPIO_REC_AL(GPP_E8, CROS_GPIO_DEVICE_NAME),
 271         CROS_GPIO_WP_AH(GPP_E15, CROS_GPIO_DEVICE_NAME),
 272 };
 273
 274 DECLARE_CROS_GPIOS(cros_gpios);