src/mainboard/google/slippy/variants/leon/overridetree.cb

   1 chip northbridge/intel/haswell
   2
   3         register "panel_cfg" = "{
   4                 .up_delay_ms            =  40,
   5                 .down_delay_ms          =  15,
   6                 .cycle_delay_ms         = 400,
   7                 .backlight_on_delay_ms  = 210,
   8                 .backlight_off_delay_ms = 210,
   9                 .backlight_pwm_hz       = 200,
  10         }"
  11
  12         device domain 0 on
  13
  14                 chip southbridge/intel/lynxpoint
  15
  16                         register "sata_devslp_disable" = "0x1"
  17
  18                         # DTLE DATA / EDGE values
  19                         register "sata_port0_gen3_dtle" = "0x5"
  20                         register "sata_port1_gen3_dtle" = "0x5"
  21
  22                         # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
  23                         register "icc_clock_disable" = "0x013c0000"
  24
  25                         device pci 1f.3 on # SMBus
  26                                 chip drivers/i2c/rtd2132
  27                                         # Panel Power Timings (1 ms units)
  28                                         # Note: the panel Tx timings are very
  29                                         # different from the LVDS bridge
  30                                         # Tx timing settings. Below is a mapping
  31                                         # for RTD2132 -> Panel timings.
  32                                         # T1 = T2
  33                                         # T2 = T8 + T10 + T12
  34                                         # T3 = T14
  35                                         # T4 = T15
  36                                         # T5 = T9 + T11 + T13
  37                                         # T6 = T3
  38                                         # T7 = T4
  39                                         register "t1" = "0x14"
  40                                         register "t2" = "0xdc"
  41                                         register "t3" = "0x0e"
  42                                         register "t4" = "0x02"
  43                                         register "t5" = "0xdc"
  44                                         register "t6" = "0x14"
  45                                         register "t7" = "0x208"
  46                                         # LVDS Swap settings are normal.
  47                                         register "lvds_swap" = "0"
  48                                         # Enable Spread Sprectrum at 0.5%
  49                                         register "sscg_percent" = "0x05"
  50                                         device i2c 35 on end # (8bit address: 0x6A)
  51                                 end # rtd2132
  52                         end # SMBus
  53                 end
  54         end
  55 end