1 chip northbridge
/intel
/haswell
3 register
"panel_cfg" = "{
7 .backlight_on_delay_ms = 1,
8 .backlight_off_delay_ms = 200,
9 .backlight_pwm_hz = 200,
14 chip southbridge
/intel
/lynxpoint
16 device pci
1f
.2 on # SATA Controller
17 register
"sata_devslp_disable" = "0x1"
19 # DTLE DATA
/ EDGE values
20 register
"sata_port0_gen3_dtle" = "0x5"
21 register
"sata_port1_gen3_dtle" = "0x5"
24 device pci
16.0 on # Management Engine Interface
1
25 # Disable PCIe CLKOUT
2-5 and CLKOUT_XDP
26 register
"icc_clock_disable" = "0x013c0000"