mainboard/intel/avenuecity_crb: Update full IIO configuration
[coreboot2.git] / src / mainboard / google / smaug / gpio.h
blob58bcfc431a07dae203036ebb01b28482e9d90ea6
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #ifndef __MAINBOARD_GOOGLE_SMAUG_GPIO_H__
4 #define __MAINBOARD_GOOGLE_SMAUG_GPIO_H__
6 #include <gpio.h>
7 #include <base3.h>
9 /* Board ID definitions. */
10 enum {
11 BOARD_REV0 = BASE3(0, 0),
12 BOARD_REV1 = BASE3(0, 1),
13 BOARD_REV2 = BASE3(0, Z),
14 BOARD_REV3 = BASE3(1, 0),
15 BOARD_REV4 = BASE3(1, 1),
16 BOARD_REV5 = BASE3(1, Z),
17 BOARD_REV6 = BASE3(Z, 0),
18 BOARD_REV7 = BASE3(Z, 1),
19 BOARD_REV8 = BASE3(Z, Z),
21 BOARD_ID_PROTO_0 = BOARD_REV0,
22 BOARD_ID_PROTO_1 = BOARD_REV1,
23 BOARD_ID_EVT = BOARD_REV2,
24 BOARD_ID_DVT = BOARD_REV3,
25 BOARD_ID_PVT = BOARD_REV4,
26 BOARD_ID_MP = BOARD_REV5,
29 enum {
30 /* Board ID related GPIOS. */
31 BD_ID0 = GPIO(K0),
32 BD_ID1 = GPIO(K1),
34 /* Warm reset */
35 AP_SYS_RESET_L = GPIO(M5),
37 /* Write Protect */
38 SPI_1V8_WP_L = GPIO(K2),
39 WRITE_PROTECT_L = SPI_1V8_WP_L,
41 /* Power button */
42 BTN_AP_PWR_L = GPIO(X5),
43 POWER_BUTTON = BTN_AP_PWR_L,
45 /* EC in RW signal */
46 EC_IN_RW = GPIO(E3),
48 /* Panel related GPIOs */
49 LCD_EN = GPIO(V1),
50 LCD_RST_L = GPIO(V2),
51 EN_VDD18_LCD = GPIO(V3),
52 EN_VDD_LCD = GPIO(V4),
55 #endif /* __MAINBOARD_GOOGLE_SMAUG_GPIO_H__ */