src/mainboard/google/zork/variants/dirinboz/gpio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <baseboard/gpio.h>
   4 #include <baseboard/variants.h>
   5 #include <gpio.h>
   6 #include <ec/google/chromeec/ec.h>
   7
   8 static const struct soc_amd_gpio bid_1_gpio_set_stage_ram[] = {
   9         /* PEN_DETECT_ODL - no used */
  10         PAD_NC(GPIO_4),
  11         /* PEN_POWER_EN - no used */
  12         PAD_NC(GPIO_5),
  13         /* TP */
  14         PAD_NC(GPIO_32),
  15         /* EN_DEV_BEEP_L */
  16         PAD_GPO(GPIO_89, HIGH),
  17         /* USI_RESET */
  18         PAD_GPO(GPIO_140, HIGH),
  19 };
  20
  21 static const struct soc_amd_gpio dirinboz_gpio_set_stage_ram[] = {
  22         /* PEN_DETECT_ODL - no used */
  23         PAD_NC(GPIO_4),
  24         /* PEN_POWER_EN - no used */
  25         PAD_NC(GPIO_5),
  26 };
  27
  28 const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
  29 {
  30         uint32_t board_version;
  31
  32         /*
  33          * If board version cannot be read, assume that this is an older revision of the board
  34          * and so apply overrides. If board version is provided by the EC, then apply overrides
  35          * if version < 2.
  36          */
  37         if (google_chromeec_cbi_get_board_version(&board_version) != 0)
  38                 board_version = 1;
  39
  40         if (board_version < 2) {
  41                 *size = ARRAY_SIZE(bid_1_gpio_set_stage_ram);
  42                 return bid_1_gpio_set_stage_ram;
  43         }
  44
  45         *size = ARRAY_SIZE(dirinboz_gpio_set_stage_ram);
  46         return dirinboz_gpio_set_stage_ram;
  47 }