src/mainboard/intel/avenuecity_crb/config/iio.c

   1 /* SPDX-License-Identifier: GPL-2.0-or-later */
   2
   3 #include <soc/iio.h>
   4
   5 static const struct iio_pe_config iio_config_table[] = {
   6         /*
   7          * CB_IIO_BIFURCATE_x8x2x2x2x2 is first set to indicate how the IIO is bifurcated
   8          * then port settings are listed accordingly. The minimal port elements are x2.
   9          * If an x8 port is enabled, the neighboring 3 x2 port elements needs to be
  10          * disabled.
  11          */
  12         {_IIO_PE_CFG_STRUCT(0x0, PE0, CB_IIO_BIFURCATE_x8x2x2x2x2, PE_TYPE_PCIE) {
  13                 /* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
  14                 _IIO_PORT_CFG_STRUCT_BASIC_X8(0x0, 0x4B, 0x1),
  15                 _IIO_PORT_CFG_STRUCT_DISABLED,
  16                 _IIO_PORT_CFG_STRUCT_DISABLED,
  17                 _IIO_PORT_CFG_STRUCT_DISABLED,
  18                 _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x2),
  19                 _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x3),
  20                 _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x4),
  21                 _IIO_PORT_CFG_STRUCT_BASIC_X2(0x0, 0x4B, 0x5),
  22         }},
  23
  24         {_IIO_PE_CFG_STRUCT(0x0, PE1, CB_IIO_BIFURCATE_x16xxxxx, PE_TYPE_PCIE) {
  25                 /* _IIO_PORT_CFG_STRUCT_BASIC(sltpls, sltplv, psn) */
  26                 _IIO_PORT_CFG_STRUCT_BASIC_X16(0x0, 0x4B, 0x6),
  27                 _IIO_PORT_CFG_STRUCT_DISABLED,
  28                 _IIO_PORT_CFG_STRUCT_DISABLED,
  29                 _IIO_PORT_CFG_STRUCT_DISABLED,
  30                 _IIO_PORT_CFG_STRUCT_DISABLED,
  31                 _IIO_PORT_CFG_STRUCT_DISABLED,
  32                 _IIO_PORT_CFG_STRUCT_DISABLED,
  33                 _IIO_PORT_CFG_STRUCT_DISABLED,
  34         }},
  35
  36         _IIO_PE_CFG_DISABLED(0x0, PE2),
  37         _IIO_PE_CFG_DISABLED(0x0, PE3),
  38         _IIO_PE_CFG_DISABLED(0x0, PE4),
  39         _IIO_PE_CFG_DISABLED(0x0, PE5),
  40         _IIO_PE_CFG_DISABLED(0x0, PEa),
  41         _IIO_PE_CFG_DISABLED(0x0, PEb),
  42         _IIO_PE_CFG_DISABLED(0x0, PEc),
  43         _IIO_PE_CFG_DISABLED(0x0, PEd),
  44
  45         _IIO_PE_CFG_DISABLED(0x1, PE0),
  46         _IIO_PE_CFG_DISABLED(0x1, PE1),
  47         _IIO_PE_CFG_DISABLED(0x1, PE2),
  48         _IIO_PE_CFG_DISABLED(0x1, PE3),
  49         _IIO_PE_CFG_DISABLED(0x1, PE4),
  50         _IIO_PE_CFG_DISABLED(0x1, PE5),
  51         _IIO_PE_CFG_DISABLED(0x1, PEa),
  52         _IIO_PE_CFG_DISABLED(0x1, PEb),
  53         _IIO_PE_CFG_DISABLED(0x1, PEc),
  54         _IIO_PE_CFG_DISABLED(0x1, PEd),
  55 };
  56
  57 const struct iio_pe_config *get_iio_config_table(int *size)
  58 {
  59         *size = ARRAY_SIZE(iio_config_table);
  60         return iio_config_table;
  61 }