mainboard/intel/avenuecity_crb: Update full IIO configuration
[coreboot2.git] / src / mainboard / kontron / 986lcd-m / mptable.c
blob5ee3288e7781e0e79d94ed2f768b4c3a6818e467
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 #include <device/device.h>
4 #include <arch/smp/mpspec.h>
5 #include <arch/ioapic.h>
7 static void *smp_write_config_table(void *v)
9 struct mp_config_table *mc;
10 struct device *riser = NULL, *firewire = NULL;
11 int firewire_bus = 0, riser_bus = 0, isa_bus;
13 mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
15 mptable_init(mc);
17 smp_write_processors(mc);
19 firewire = dev_find_device(0x104c, 0x8023, 0);
20 if (firewire) {
21 firewire_bus = firewire->upstream->secondary;
24 /* If a riser card is used, this riser is detected on bus 4, so its secondary bus is the */
25 /* highest bus number on the pci bus. */
26 riser = dev_find_device(0x3388, 0x0021, 0);
27 if (!riser)
28 riser = dev_find_device(0x3388, 0x0022, 0);
29 if (riser) {
30 riser_bus = riser->downstream->secondary;
33 mptable_write_buses(mc, NULL, &isa_bus);
35 /* I/O APICs: APIC ID Version State Address */
36 u8 ioapic_id = smp_write_ioapic_from_hw(mc, IO_APIC_ADDR);
38 /* Legacy Interrupts */
39 mptable_add_isa_interrupts(mc, isa_bus, ioapic_id, 0);
41 /* Builtin devices on Bus 0 */
42 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x01, 0, ioapic_id, 0x10);
43 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x02, 0, ioapic_id, 0x10);
44 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1f, 1, ioapic_id, 0x13);
45 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 0, ioapic_id, 0x17);
46 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 1, ioapic_id, 0x13);
47 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 2, ioapic_id, 0x12);
48 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1d, 3, ioapic_id, 0x10);
49 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1b, 0, ioapic_id, 0x10);
50 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 0, ioapic_id, 0x10);
51 smp_write_pci_intsrc(mc, mp_INT, 0x0, 0x1c, 1, ioapic_id, 0x11);
53 /* Internal PCI bus (Firewire, PCI slot) */
54 if (firewire) {
55 smp_write_pci_intsrc(mc, mp_INT, firewire_bus, 0x00, 0, ioapic_id, 0x10);
56 smp_write_pci_intsrc(mc, mp_INT, firewire_bus, 0x01, 0, ioapic_id, 0x14);
59 if (riser) {
60 /* Old riser card */
61 /* riser slot top 5:8.0 */
62 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x08, 0, ioapic_id, 0x14);
63 /* riser slot middle 5:9.0 */
64 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x09, 0, ioapic_id, 0x15);
65 /* riser slot bottom 5:a.0 */
66 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0a, 0, ioapic_id, 0x16);
68 /* New Riser Card */
69 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0c, 0, ioapic_id, 0x14);
70 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0d, 0, ioapic_id, 0x15);
71 smp_write_pci_intsrc(mc, mp_INT, riser_bus, 0x0e, 0, ioapic_id, 0x16);
74 /* PCIe slot */
75 smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 0, ioapic_id, 0x10);
76 smp_write_pci_intsrc(mc, mp_INT, 0x1, 0x00, 1, ioapic_id, 0x11);
78 /* Onboard Ethernet */
79 smp_write_pci_intsrc(mc, mp_INT, 0x2, 0x00, 0, ioapic_id, 0x10);
81 /* Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
82 mptable_lintsrc(mc, isa_bus);
84 /* Compute the checksums */
85 return mptable_finalize(mc);
88 unsigned long write_smp_table(unsigned long addr)
90 void *v;
91 v = smp_write_floating_table(addr, 1);
92 return (unsigned long)smp_write_config_table(v);